library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity hellfire_cpu_if is
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entity hfrisc_soc is
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generic(
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generic(
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address_width: integer := 14;
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address_width: integer := 14;
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memory_file : string := "code.txt";
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memory_file : string := "code.txt";
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uart_support : string := "yes"
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uart_support : string := "yes"
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);
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);
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port ( clk_in: in std_logic;
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port ( clk_in: in std_logic;
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reset_in: in std_logic;
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reset_in: in std_logic;
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int_in: in std_logic;
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int_in: in std_logic;
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uart_read: in std_logic;
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uart_read: in std_logic;
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uart_write: out std_logic
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uart_write: out std_logic
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);
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);
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end hellfire_cpu_if;
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end hfrisc_soc;
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architecture interface of hellfire_cpu_if is
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architecture top_level of hfrisc_soc is
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signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
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signal clock, boot_enable, ram_enable_n, stall, stall_cpu, busy_cpu, irq_cpu, irq_ack_cpu, data_access_cpu, ram_dly, rff1, reset: std_logic;
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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begin
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begin
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-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
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-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
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process (reset_in, clk_in, clock)
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process (reset_in, clk_in, clock)
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begin
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begin
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if reset_in = '1' then
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if reset_in = '1' then
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clock <= '0';
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clock <= '0';
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else
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else
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if clk_in'event and clk_in='1' then
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if clk_in'event and clk_in='1' then
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clock <= not clock;
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clock <= not clock;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- reset synchronizer
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-- reset synchronizer
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process (clock, reset_in)
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process (clock, reset_in)
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begin
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begin
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if (reset_in = '1') then
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if (reset_in = '1') then
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rff1 <= '1';
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rff1 <= '1';
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reset <= '1';
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reset <= '1';
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elsif (clock'event and clock = '1') then
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elsif (clock'event and clock = '1') then
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rff1 <= '0';
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rff1 <= '0';
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reset <= rff1;
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reset <= rff1;
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end if;
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end if;
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end process;
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end process;
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process (reset, clock, ext_irq, ram_enable_n)
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process (reset, clock, ext_irq, ram_enable_n)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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ram_dly <= '0';
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ram_dly <= '0';
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ext_irq <= x"00";
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ext_irq <= x"00";
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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ram_dly <= not ram_enable_n;
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ram_dly <= not ram_enable_n;
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ext_irq <= "0000000" & int_in;
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ext_irq <= "0000000" & int_in;
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end if;
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end if;
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end process;
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end process;
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stall <= '0';
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stall <= '0';
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boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
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boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
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ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
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ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
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data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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data_w_n_ram <= not data_we;
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data_w_n_ram <= not data_we;
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-- HF-RISC core
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-- HF-RISC core
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core: entity work.datapath
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core: entity work.datapath
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port map( clock => clock,
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port map( clock => clock,
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reset => reset,
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reset => reset,
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stall => stall_cpu,
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stall => stall_cpu,
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busy => busy_cpu,
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irq_vector => irq_vector_cpu,
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irq_vector => irq_vector_cpu,
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irq => irq_cpu,
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irq => irq_cpu,
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irq_ack => irq_ack_cpu,
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irq_ack => irq_ack_cpu,
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inst_addr => inst_addr_cpu,
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address => address_cpu,
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inst_in => inst_in_cpu,
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data_addr => data_addr_cpu,
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data_in => data_in_cpu,
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data_in => data_in_cpu,
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data_out => data_out_cpu,
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data_out => data_out_cpu,
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data_w => data_w_cpu,
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data_w => data_w_cpu,
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data_access => data_access_cpu
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data_access => data_access_cpu
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);
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);
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-- peripherals / busmux logic
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-- peripherals / busmux logic
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peripherals_busmux: entity work.busmux
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peripherals_busmux: entity work.busmux
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generic map(
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generic map(
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uart_support => uart_support
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uart_support => uart_support
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)
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)
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port map(
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port map(
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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stall => stall,
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stall => stall,
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stall_cpu => stall_cpu,
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stall_cpu => stall_cpu,
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busy_cpu => busy_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_cpu => irq_cpu,
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irq_cpu => irq_cpu,
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irq_ack_cpu => irq_ack_cpu,
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irq_ack_cpu => irq_ack_cpu,
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inst_addr_cpu => inst_addr_cpu,
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address_cpu => address_cpu,
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inst_in_cpu => inst_in_cpu,
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data_addr_cpu => data_addr_cpu,
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data_in_cpu => data_in_cpu,
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data_in_cpu => data_in_cpu,
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data_out_cpu => data_out_cpu,
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data_out_cpu => data_out_cpu,
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data_w_cpu => data_w_cpu,
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data_w_cpu => data_w_cpu,
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data_access_cpu => data_access_cpu,
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data_access_cpu => data_access_cpu,
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addr_mem => address,
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addr_mem => address,
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data_read_mem => data_read,
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data_read_mem => data_read,
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data_write_mem => data_write,
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data_write_mem => data_write,
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data_we_mem => data_we,
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data_we_mem => data_we,
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extio_in => ext_irq,
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extio_in => ext_irq,
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extio_out => open,
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extio_out => open,
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uart_read => uart_read,
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uart_read => uart_read,
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uart_write => uart_write
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uart_write => uart_write
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);
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);
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-- instruction and data memory (boot RAM)
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-- instruction and data memory (boot RAM)
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boot_ram: entity work.ram
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boot_ram: entity work.ram
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generic map (memory_type => "DEFAULT")
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generic map (memory_type => "DEFAULT")
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port map (
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port map (
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clk => clock,
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clk => clock,
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enable => boot_enable,
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enable => boot_enable,
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write_byte_enable => "0000",
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write_byte_enable => "0000",
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address => address(31 downto 2),
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address => address(31 downto 2),
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data_write => (others => '0'),
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data_write => (others => '0'),
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data_read => data_read_boot
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data_read => data_read_boot
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);
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);
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-- instruction and data memory (external RAM)
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-- instruction and data memory (external RAM)
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memory0lb: entity work.bram
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memory0lb: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 0)
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bank => 0)
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port map(
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port map(
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clk => clock,
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clk => clock,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(0),
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we_n => data_w_n_ram(0),
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data_i => data_write(7 downto 0),
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data_i => data_write(7 downto 0),
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data_o => data_read_ram(7 downto 0)
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data_o => data_read_ram(7 downto 0)
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);
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);
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memory0ub: entity work.bram
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memory0ub: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 1)
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bank => 1)
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port map(
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port map(
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clk => clock,
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clk => clock,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(1),
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we_n => data_w_n_ram(1),
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data_i => data_write(15 downto 8),
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data_i => data_write(15 downto 8),
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data_o => data_read_ram(15 downto 8)
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data_o => data_read_ram(15 downto 8)
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);
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);
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memory1lb: entity work.bram
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memory1lb: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 2)
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bank => 2)
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port map(
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port map(
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clk => clock,
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clk => clock,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(2),
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we_n => data_w_n_ram(2),
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data_i => data_write(23 downto 16),
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data_i => data_write(23 downto 16),
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data_o => data_read_ram(23 downto 16)
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data_o => data_read_ram(23 downto 16)
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);
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);
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memory1ub: entity work.bram
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memory1ub: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 3)
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bank => 3)
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port map(
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port map(
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clk => clock,
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clk => clock,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(3),
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we_n => data_w_n_ram(3),
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data_i => data_write(31 downto 24),
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data_i => data_write(31 downto 24),
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data_o => data_read_ram(31 downto 24)
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data_o => data_read_ram(31 downto 24)
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);
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);
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end interface;
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end top_level;
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