-- HF-RISCV v1.3
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-- HF-RISCV v1.4
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-- Sergio Johann Filho, 2015 - 2016
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-- Sergio Johann Filho, 2015 - 2016
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--
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--
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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-- books), double clocked or operating on the opposite edge. Pipeline stages are:
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-- books), double clocked or operating on the opposite edge. Pipeline stages are:
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--
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--
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-- FETCH: instruction memory is accessed (address is PC), data becomes available in one cycle. PC is updated.
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-- FETCH: instruction memory is accessed (address is PC), data becomes available in one cycle. PC is updated.
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-- DECODE: an instruction is fed into the decoding / control logic and values are registered for the next
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-- DECODE: an instruction is fed into the decoding / control logic and values are registered for the next
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-- stage. pipeline stalls, as well as bubble insertion is performed in this stage.
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-- stage. pipeline stalls, as well as bubble insertion is performed in this stage.
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-- EXECUTE: the register file is accessed and the ALU calculates the result. data access is performed (loads
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-- EXECUTE: the register file is accessed and the ALU calculates the result. data access is performed (loads
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-- and stores) or simply the result (or pc) is written to the register file (normal operations). branch target
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-- and stores) or simply the result (or pc) is written to the register file (normal operations). branch target
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-- and outcome are calculated.
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-- and outcome are calculated.
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--
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--
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-- *This design is a compromise between performance, area and complexity.
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-- *This design is a compromise between performance, area and complexity.
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-- *Only the RV32I base instruction set is implemented. FENCE and SYSTEM instructions are missing. SYSTEM
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-- *Only the RV32I base instruction set is implemented. FENCE and SYSTEM instructions are missing. SYSTEM
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-- instructions always trap the processor and can be handled in software.
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-- instructions always trap the processor and can be handled in software.
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-- *Memory is accessed in little endian mode.
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-- *Memory is accessed in little endian mode.
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-- *No co-processor is implemented and all peripherals are memory mapped.
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-- *No co-processor is implemented and all peripherals are memory mapped.
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-- *Loads and stores take 2/1 cycles with separated code/data memories and 3 cycles otherwise. This version is organized
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-- *Loads and stores take 3 cycles. This version is organized as a Von Neumann machine, so there is only one
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-- as a Von Neumann machine, so there is only one memory interface that is shared betweeen code and data accesses.
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-- memory interface that is shared betweeen code and data accesses.
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-- *Branches have a 1 cycle delay (not taken) or 3 cycle dalay (taken), including two branch delay slots.
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-- *Branches have a 1 cycle delay (not taken) or 3 cycle dalay (taken), including two branch delay slots.
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-- This is a side effect of the pipeline refill and memory access policy. All other instructions are single
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-- This is a side effect of the pipeline refill and memory access policy. All other instructions are single
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-- cycle. No branch predictor is implemented (default branch target is 'not taken').
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-- cycle. No branch predictor is implemented (default branch target is 'not taken').
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-- *Interrupts are handled using VECTOR, CAUSE, MASK, STATUS and EPC registers. The VECTOR register is used to hold
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-- *Interrupts are handled using VECTOR, CAUSE, MASK, STATUS and EPC registers. The VECTOR register is used to hold
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-- the address of the default (non-vectored) interrupt handler. The CAUSE register is read only and peripheral
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-- the address of the default (non-vectored) interrupt handler. The CAUSE register is read only and peripheral
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-- interrupt lines are connected to this register. The MASK register is read/write and holds the interrupt mask
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-- interrupt lines are connected to this register. The MASK register is read/write and holds the interrupt mask
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-- for the CAUSE register. The interrupt STATUS register is automatically cleared on interrupts, and is set by
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-- for the CAUSE register. The interrupt STATUS register is automatically cleared on interrupts, and is set by
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-- software when returning from interrupts - this works as a global interrupt enable/disable flag. This register is
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-- software when returning from interrupts - this works as a global interrupt enable/disable flag. This register is
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-- read and write capable, so it can also be cleared by software. Setting this register just before returning
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-- read and write capable, so it can also be cleared by software. Setting this register just before returning
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-- from interrupts (enable is delayed in a few cycles) re-enables interrupts. The EPC register holds the program
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-- from interrupts (enable is delayed in a few cycles) re-enables interrupts. The EPC register holds the program
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-- counter when the processor is interrupted (we should re-execute the last instruction (EPC-4), as it was not
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-- counter when the processor is interrupted (we should re-execute the last instruction (EPC-4), as it was not
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-- commited yet). EPC is a read only register, and is used to return from an interrupt using simple LW / JR
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-- commited yet). EPC is a read only register, and is used to return from an interrupt using simple LW / JR
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-- instructions. As an interrupt is accepted, the processor jumps to VECTOR address where the first level of irq
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-- instructions. As an interrupt is accepted, the processor jumps to VECTOR address where the first level of irq
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-- handling is done. A second level handler (in C) implements the interrupt priority mechanism and calls the
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-- handling is done. A second level handler (in C) implements the interrupt priority mechanism and calls the
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-- appropriate ISR for each interrupt.
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-- appropriate ISR for each interrupt.
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-- *Built in peripherals: running counter (32 bit), two counter comparators (32 and 24 bit), I/O ports and UART. the
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-- *Built in peripherals: running counter (32 bit), two counter comparators (32 and 24 bit), I/O ports and UART. the
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-- UART baud rate is defined in a 16 bit divisor register. Two counter bits (bits 18 and 16 and their complements) are
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-- UART baud rate is defined in a 16 bit divisor register. Two counter bits (bits 18 and 16 and their complements) are
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-- tied to interrupt lines, so are the two counter comparators and the UART.
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-- tied to interrupt lines, so are the two counter comparators and the UART.
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--
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--
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-- Memory map:
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-- Memory map:
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--
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--
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-- ROM 0x00000000 - 0x1fffffff (512MB)
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-- ROM 0x00000000 - 0x1fffffff (512MB)
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-- System 0x20000000 - 0x3fffffff (512MB)
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-- System 0x20000000 - 0x3fffffff (512MB)
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-- SRAM 0x40000000 - 0x5fffffff (512MB)
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-- SRAM 0x40000000 - 0x5fffffff (512MB)
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-- External RAM / device 0x60000000 - 0x9fffffff (1GB)
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-- External RAM / device 0x60000000 - 0x9fffffff (1GB)
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-- External RAM / device 0xa0000000 - 0xdfffffff (1GB) (uncached)
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-- External RAM / device 0xa0000000 - 0xdfffffff (1GB) (uncached)
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-- External Peripheral 0xe0000000 - 0xefffffff (256MB) (uncached)
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-- External Peripheral 0xe0000000 - 0xefffffff (256MB) (uncached)
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-- Peripheral (core) 0xf0000000 - 0xf7ffffff (128MB) (uncached)
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-- Peripheral (core) 0xf0000000 - 0xf7ffffff (128MB) (uncached)
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-- Peripheral (extended) 0xf8000000 - 0xffffffff (128MB) (uncached)
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-- Peripheral (extended) 0xf8000000 - 0xffffffff (128MB) (uncached)
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--
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--
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-- IRQ_VECTOR 0xf0000000
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-- IRQ_VECTOR 0xf0000000
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-- IRQ_CAUSE 0xf0000010
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-- IRQ_CAUSE 0xf0000010
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-- IRQ_MASK 0xf0000020
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-- IRQ_MASK 0xf0000020
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-- IRQ_STATUS 0xf0000030
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-- IRQ_STATUS 0xf0000030
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-- IRQ_EPC 0xf0000040
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-- IRQ_EPC 0xf0000040
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-- COUNTER 0xf0000050
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-- COUNTER 0xf0000050
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-- COMPARE 0xf0000060
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-- COMPARE 0xf0000060
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-- COMPARE2 0xf0000070
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-- COMPARE2 0xf0000070
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-- EXTIO_IN 0xf0000080
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-- EXTIO_IN 0xf0000080
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-- EXTIO_OUT 0xf0000090
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-- EXTIO_OUT 0xf0000090
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-- DEBUG 0xf00000d0
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-- DEBUG 0xf00000d0
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-- UART_WRITE / UART_READ 0xf00000e0
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-- UART_WRITE / UART_READ 0xf00000e0
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-- UART_DIVISOR 0xf00000f0
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-- UART_DIVISOR 0xf00000f0
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--
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--
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-- Interrupt masks:
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-- Interrupt masks:
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--
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--
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-- IRQ_COUNTER 0x0001 (bit 18 of the counter is set)
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-- IRQ_COUNTER 0x0001 (bit 18 of the counter is set)
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-- IRQ_COUNTER_NOT 0x0002 (bit 18 of the counter is clear)
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-- IRQ_COUNTER_NOT 0x0002 (bit 18 of the counter is clear)
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-- IRQ_COUNTER2 0x0004 (bit 16 of the counter is set)
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-- IRQ_COUNTER2 0x0004 (bit 16 of the counter is set)
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-- IRQ_COUNTER2_NOT 0x0008 (bit 16 of the counter is clear)
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-- IRQ_COUNTER2_NOT 0x0008 (bit 16 of the counter is clear)
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-- IRQ_COMPARE 0x0010 (counter is equal to compare, clears irq when updated)
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-- IRQ_COMPARE 0x0010 (counter is equal to compare, clears irq when updated)
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-- IRQ_COMPARE2 0x0020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
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-- IRQ_COMPARE2 0x0020 (counter bits 23 to 0 are equal to compare2, clears irq when updated)
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-- IRQ_UART_READ_AVAILABLE 0x0040 (there is data available for reading on the UART)
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-- IRQ_UART_READ_AVAILABLE 0x0040 (there is data available for reading on the UART)
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-- IRQ_UART_WRITE_AVAILABLE 0x0080 (UART is not busy)
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-- IRQ_UART_WRITE_AVAILABLE 0x0080 (UART is not busy)
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-- EXT_IRQ0 0x0100 (external interrupts on extio_in, 'high' level triggered)
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-- EXT_IRQ0 0x0100 (external interrupts on extio_in, 'high' level triggered)
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-- EXT_IRQ1 0x0200
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-- EXT_IRQ1 0x0200
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-- EXT_IRQ2 0x0400
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-- EXT_IRQ2 0x0400
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-- EXT_IRQ3 0x0800
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-- EXT_IRQ3 0x0800
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-- EXT_IRQ4 0x1000
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-- EXT_IRQ4 0x1000
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-- EXT_IRQ5 0x2000
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-- EXT_IRQ5 0x2000
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-- EXT_IRQ6 0x4000
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-- EXT_IRQ6 0x4000
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-- EXT_IRQ7 0x8000
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-- EXT_IRQ7 0x8000
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity busmux is
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entity busmux is
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generic(
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generic(
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log_file: string := "UNUSED"; -- options are "out.txt" and "UNUSED"
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log_file: string := "UNUSED"; -- options are "out.txt" and "UNUSED"
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uart_support: string := "no" -- options are "yes" and "no".
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uart_support: string := "no" -- options are "yes" and "no".
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);
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);
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port ( clock: in std_logic;
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port ( clock: in std_logic;
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reset: in std_logic;
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reset: in std_logic;
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stall: in std_logic;
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stall: in std_logic;
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stall_cpu: out std_logic;
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stall_cpu: out std_logic;
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busy_cpu: out std_logic;
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irq_vector_cpu: out std_logic_vector(31 downto 0);
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irq_vector_cpu: out std_logic_vector(31 downto 0);
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irq_cpu: out std_logic;
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irq_cpu: out std_logic;
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irq_ack_cpu: in std_logic;
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irq_ack_cpu: in std_logic;
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exception_cpu: in std_logic;
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exception_cpu: in std_logic;
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inst_addr_cpu: in std_logic_vector(31 downto 0);
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address_cpu: in std_logic_vector(31 downto 0);
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inst_in_cpu: out std_logic_vector(31 downto 0);
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data_addr_cpu: in std_logic_vector(31 downto 0);
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data_in_cpu: out std_logic_vector(31 downto 0);
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data_in_cpu: out std_logic_vector(31 downto 0);
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data_out_cpu: in std_logic_vector(31 downto 0);
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data_out_cpu: in std_logic_vector(31 downto 0);
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data_w_cpu: in std_logic_vector(3 downto 0);
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data_w_cpu: in std_logic_vector(3 downto 0);
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data_access_cpu: in std_logic;
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data_access_cpu: in std_logic;
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addr_mem: out std_logic_vector(31 downto 0);
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addr_mem: out std_logic_vector(31 downto 0);
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data_read_mem: in std_logic_vector(31 downto 0);
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data_read_mem: in std_logic_vector(31 downto 0);
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data_write_mem: out std_logic_vector(31 downto 0);
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data_write_mem: out std_logic_vector(31 downto 0);
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data_we_mem: out std_logic_vector(3 downto 0);
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data_we_mem: out std_logic_vector(3 downto 0);
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extio_in: in std_logic_vector(7 downto 0);
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extio_in: in std_logic_vector(7 downto 0);
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extio_out: out std_logic_vector(7 downto 0);
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extio_out: out std_logic_vector(7 downto 0);
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uart_read: in std_logic;
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uart_read: in std_logic;
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uart_write: out std_logic
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uart_write: out std_logic
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);
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);
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end busmux;
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end busmux;
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architecture arch of busmux is
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architecture arch of busmux is
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signal write_enable: std_logic;
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signal write_enable: std_logic;
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signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
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signal irq_cause, irq_mask_reg, uart_divisor: std_logic_vector(15 downto 0);
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signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
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signal irq_status_reg, extio_out_reg: std_logic_vector(7 downto 0);
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signal irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
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signal periph_data, irq_vector_reg, irq_epc_reg, compare_reg, counter_reg: std_logic_vector(31 downto 0);
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
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type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
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signal pulse_state: pulse_state_type;
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signal pulse_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal periph_access, periph_access_we, data_access_cpu_dly, data_access_cpu_dly2: std_logic;
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signal periph_access, periph_access_dly, periph_access_we: std_logic;
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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begin
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begin
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-- address decoder, read from peripheral registers
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-- address decoder, read from peripheral registers
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process(data_addr_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, compare_reg, compare2_reg, counter_reg, data_read_uart, uart_divisor, data_read_mem, extio_in, extio_out_reg)
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process(clock, reset, periph_access, address_cpu, irq_vector_reg, irq_cause, irq_mask_reg, irq_status_reg, irq_epc_reg, compare_reg, compare2_reg, counter_reg, data_read_uart, uart_divisor, data_read_mem, extio_in, extio_out_reg)
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begin
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begin
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case data_addr_cpu(31 downto 27) is
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if reset = '1' then
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when "11110" => -- Peripherals (f000 0000 - f7ff ffff)
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periph_data <= (others => '0');
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case data_addr_cpu(7 downto 4) is
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elsif clock'event and clock = '1' then
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if periph_access = '1' then
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case address_cpu(7 downto 4) is
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when "0000" => -- IRQ_VECTOR (RW)
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when "0000" => -- IRQ_VECTOR (RW)
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data_in_cpu <= irq_vector_reg;
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periph_data <= irq_vector_reg;
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when "0001" => -- IRQ_CAUSE (RO)
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when "0001" => -- IRQ_CAUSE (RO)
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data_in_cpu <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & x"0000";
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periph_data <= irq_cause(7 downto 0) & irq_cause(15 downto 8) & x"0000";
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when "0010" => -- IRQ_MASK (RW)
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when "0010" => -- IRQ_MASK (RW)
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data_in_cpu <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & x"0000";
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periph_data <= irq_mask_reg(7 downto 0) & irq_mask_reg(15 downto 8) & x"0000";
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when "0011" => -- IRQ_STATUS (RW)
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when "0011" => -- IRQ_STATUS (RW)
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data_in_cpu <= irq_status_reg & x"000000";
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periph_data <= irq_status_reg & x"000000";
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when "0100" => -- IRQ_EPC (RO)
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when "0100" => -- IRQ_EPC (RO)
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data_in_cpu <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
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periph_data <= irq_epc_reg(7 downto 0) & irq_epc_reg(15 downto 8) & irq_epc_reg(23 downto 16) & irq_epc_reg(31 downto 24);
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when "0101" => -- COUNTER (RO)
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when "0101" => -- COUNTER (RO)
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data_in_cpu <= counter_reg(7 downto 0) & counter_reg(15 downto 8) & counter_reg(23 downto 16) & counter_reg(31 downto 24);
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periph_data <= counter_reg(7 downto 0) & counter_reg(15 downto 8) & counter_reg(23 downto 16) & counter_reg(31 downto 24);
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when "0110" => -- IRQ_COMPARE (RW)
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when "0110" => -- IRQ_COMPARE (RW)
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data_in_cpu <= compare_reg(7 downto 0) & compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24);
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periph_data <= compare_reg(7 downto 0) & compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24);
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when "0111" => -- IRQ_COMPARE2 (RW)
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when "0111" => -- IRQ_COMPARE2 (RW)
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data_in_cpu <= compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24) & x"00";
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periph_data <= compare_reg(15 downto 8) & compare_reg(23 downto 16) & compare_reg(31 downto 24) & x"00";
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when "1000" => -- EXTIO_IN (RO)
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when "1000" => -- EXTIO_IN (RO)
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data_in_cpu <= extio_in & x"000000";
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periph_data <= extio_in & x"000000";
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when "1001" => -- EXTIO_OUT (RW)
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when "1001" => -- EXTIO_OUT (RW)
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data_in_cpu <= extio_out_reg & x"000000";
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periph_data <= extio_out_reg & x"000000";
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when "1110" => -- UART (RW)
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when "1110" => -- UART (RW)
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data_in_cpu <= data_read_uart & x"000000";
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periph_data <= data_read_uart & x"000000";
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when "1111" => -- UART_DIVISOR (RW)
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when "1111" => -- UART_DIVISOR (RW)
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data_in_cpu <= uart_divisor(7 downto 0) & uart_divisor(15 downto 8) & x"0000";
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periph_data <= uart_divisor(7 downto 0) & uart_divisor(15 downto 8) & x"0000";
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when others =>
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when others =>
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data_in_cpu <= data_read_mem;
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periph_data <= data_read_mem;
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end case;
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when others => -- ROM / RAM area, external peripherals (f800 0000 - ffff fffc)
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data_in_cpu <= data_read_mem;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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|
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inst_in_cpu <= data_read_mem;
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data_in_cpu <= data_read_mem when periph_access_dly = '0' else periph_data;
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|
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-- peripheral register logic, write to peripheral registers
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-- peripheral register logic, write to peripheral registers
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process(clock, reset, counter_reg, data_addr_cpu, data_out_cpu, periph_access, periph_access_we, irq)
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process(clock, reset, counter_reg, address_cpu, data_out_cpu, periph_access, periph_access_we, irq_ack_cpu)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_vector_reg <= x"00000000";
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irq_vector_reg <= x"00000000";
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irq_mask_reg <= x"0000";
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irq_mask_reg <= x"0000";
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irq_status_reg <= x"00";
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irq_status_reg <= x"00";
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counter_reg <= x"00000000";
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counter_reg <= x"00000000";
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compare_reg <= x"00000000";
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compare_reg <= x"00000000";
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compare_trig <= '0';
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compare_trig <= '0';
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compare2_reg <= x"000000";
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compare2_reg <= x"000000";
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compare2_trig <= '0';
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compare2_trig <= '0';
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extio_out_reg <= x"00";
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extio_out_reg <= x"00";
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uart_divisor <= x"0000";
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uart_divisor <= x"0000";
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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counter_reg <= counter_reg + 1;
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counter_reg <= counter_reg + 1;
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if compare_reg = counter_reg then
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if compare_reg = counter_reg then
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compare_trig <= '1';
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compare_trig <= '1';
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end if;
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end if;
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if compare2_reg = counter_reg(23 downto 0) then
|
if compare2_reg = counter_reg(23 downto 0) then
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compare2_trig <= '1';
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compare2_trig <= '1';
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end if;
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end if;
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if periph_access = '1' and periph_access_we = '1' then
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if periph_access = '1' and periph_access_we = '1' then
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case data_addr_cpu(7 downto 4) is
|
case address_cpu(7 downto 4) is
|
when "0000" => -- IRQ_VECTOR
|
when "0000" => -- IRQ_VECTOR
|
irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
when "0010" => -- IRQ_MASK
|
when "0010" => -- IRQ_MASK
|
irq_mask_reg <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
irq_mask_reg <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
when "0011" => -- IRQ_STATUS
|
when "0011" => -- IRQ_STATUS
|
irq_status_reg <= data_out_cpu(31 downto 24);
|
irq_status_reg <= data_out_cpu(31 downto 24);
|
when "0110" => -- IRQ_COMPARE
|
when "0110" => -- IRQ_COMPARE
|
compare_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
compare_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
compare_trig <= '0';
|
compare_trig <= '0';
|
when "0111" => -- IRQ_COMPARE2
|
when "0111" => -- IRQ_COMPARE2
|
compare2_reg <= data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
compare2_reg <= data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
compare2_trig <= '0';
|
compare2_trig <= '0';
|
when "1001" => -- EXTIO_OUT
|
when "1001" => -- EXTIO_OUT
|
extio_out_reg <= data_out_cpu(31 downto 24);
|
extio_out_reg <= data_out_cpu(31 downto 24);
|
when "1111" => -- UART_DIVISOR
|
when "1111" => -- UART_DIVISOR
|
uart_divisor <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
uart_divisor <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
|
when others =>
|
when others =>
|
end case;
|
end case;
|
end if;
|
end if;
|
if irq_ack_cpu = '1' or exception_cpu = '1' then
|
if irq_ack_cpu = '1' or exception_cpu = '1' then
|
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
|
irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- EPC register register load on interrupts
|
-- EPC register register load on interrupts
|
process(clock, reset, inst_addr_cpu, irq, irq_ack_cpu)
|
process(clock, reset, address_cpu, irq, irq_ack_cpu)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
irq_epc_reg <= x"00000000";
|
irq_epc_reg <= x"00000000";
|
elsif clock'event and clock = '1' then
|
elsif clock'event and clock = '1' then
|
if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
|
if ((irq = '1' and irq_ack_cpu = '0') or exception_cpu = '1') then
|
irq_epc_reg <= inst_addr_cpu;
|
irq_epc_reg <= address_cpu;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- interrupt state machine
|
-- interrupt state machine
|
process(clock, reset, pulse_state, interrupt, irq_status_reg, stall)
|
process(clock, reset, pulse_state, interrupt, irq_status_reg, stall)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
pulse_state <= irq_idle;
|
pulse_state <= irq_idle;
|
pulse_next_state <= irq_idle;
|
pulse_next_state <= irq_idle;
|
irq <= '0';
|
irq <= '0';
|
elsif clock'event and clock = '1' then
|
elsif clock'event and clock = '1' then
|
if stall = '0' then
|
if stall = '0' then
|
pulse_state <= pulse_next_state;
|
pulse_state <= pulse_next_state;
|
case pulse_state is
|
case pulse_state is
|
when irq_idle =>
|
when irq_idle =>
|
if interrupt = '1' and irq_status_reg(0) = '1' then
|
if interrupt = '1' and irq_status_reg(0) = '1' then
|
pulse_next_state <= irq_int;
|
pulse_next_state <= irq_int;
|
end if;
|
end if;
|
when irq_int =>
|
when irq_int =>
|
irq <= '1';
|
irq <= '1';
|
pulse_next_state <= irq_req;
|
pulse_next_state <= irq_req;
|
when irq_req =>
|
when irq_req =>
|
if irq_ack_cpu = '1' then
|
if irq_ack_cpu = '1' then
|
irq <= '0';
|
irq <= '0';
|
pulse_next_state <= irq_ackn;
|
pulse_next_state <= irq_ackn;
|
end if;
|
end if;
|
when irq_ackn =>
|
when irq_ackn =>
|
pulse_next_state <= irq_done;
|
pulse_next_state <= irq_done;
|
when irq_done =>
|
when irq_done =>
|
if irq_status_reg(0) = '1' then
|
if irq_status_reg(0) = '1' then
|
pulse_next_state <= irq_idle;
|
pulse_next_state <= irq_idle;
|
end if;
|
end if;
|
when others =>
|
when others =>
|
pulse_next_state <= irq_idle;
|
pulse_next_state <= irq_idle;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- data / peripheral access delay
|
-- data / peripheral access delay
|
process(clock, reset, irq_ack_cpu, data_access_cpu, stall)
|
process(clock, reset, irq_ack_cpu, periph_access, stall)
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
data_access_cpu_dly <= '0';
|
periph_access_dly <= '0';
|
data_access_cpu_dly2 <= '0';
|
|
elsif clock'event and clock = '1' then
|
elsif clock'event and clock = '1' then
|
if stall = '0' then
|
if stall = '0' then
|
data_access_cpu_dly2 <= data_access_cpu_dly;
|
periph_access_dly <= periph_access;
|
if data_access_cpu = '1' and data_access_cpu_dly = '0' and data_access_cpu_dly2 = '0' then
|
|
data_access_cpu_dly <= '1';
|
|
else
|
|
data_access_cpu_dly <= '0';
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
periph_access <= '1' when data_addr_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
|
periph_access <= '1' when address_cpu(31 downto 27) = "11110" and data_access_cpu = '1' else '0';
|
periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
|
periph_access_we <= '1' when periph_access <= '1' and data_w_cpu /= "0000" else '0';
|
|
|
-- memory address / write enable muxes and cpu stall logic
|
-- memory address / write enable muxes and cpu stall logic
|
addr_mem <= data_addr_cpu when data_access_cpu_dly = '0' and data_access_cpu = '1' and periph_access = '0' else inst_addr_cpu;
|
addr_mem <= address_cpu;
|
data_write_mem <= data_out_cpu;
|
data_write_mem <= data_out_cpu;
|
data_we_mem_s <= data_w_cpu when data_access_cpu_dly = '0' and data_access_cpu = '1' and periph_access = '0' else "0000";
|
data_we_mem_s <= data_w_cpu when data_access_cpu = '1' and periph_access = '0' else "0000";
|
data_we_mem <= data_we_mem_s;
|
data_we_mem <= data_we_mem_s;
|
|
|
busy_cpu <= (data_access_cpu and not data_access_cpu_dly); -- load/store: 1 wait cycle
|
|
stall_cpu <= stall;
|
stall_cpu <= stall;
|
|
|
-- interrupts and peripherals
|
-- interrupts and peripherals
|
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
|
interrupt <= '0' when (irq_cause and irq_mask_reg) = x"0000" else '1';
|
irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
|
irq_cause <= extio_in & not uart_write_busy & uart_data_avail & irq_compare2 & irq_compare & irq_counter2_not & irq_counter2 & irq_counter_not & irq_counter;
|
|
|
irq_cpu <= irq;
|
irq_cpu <= irq;
|
irq_vector_cpu <= irq_vector_reg;
|
irq_vector_cpu <= irq_vector_reg;
|
irq_counter <= counter_reg(18);
|
irq_counter <= counter_reg(18);
|
irq_counter_not <= not counter_reg(18);
|
irq_counter_not <= not counter_reg(18);
|
irq_counter2 <= counter_reg(16);
|
irq_counter2 <= counter_reg(16);
|
irq_counter2_not <= not counter_reg(16);
|
irq_counter2_not <= not counter_reg(16);
|
irq_compare <= '1' when compare_trig = '1' else '0';
|
irq_compare <= '1' when compare_trig = '1' else '0';
|
irq_compare2 <= '1' when compare2_trig = '1' else '0';
|
irq_compare2 <= '1' when compare2_trig = '1' else '0';
|
extio_out <= extio_out_reg;
|
extio_out <= extio_out_reg;
|
|
|
write_enable <= '1' when data_we_mem_s /= "0000" else '0';
|
write_enable <= '1' when data_we_mem_s /= "0000" else '0';
|
data_write_uart <= data_out_cpu(31 downto 24);
|
data_write_uart <= data_out_cpu(31 downto 24);
|
|
|
uart:
|
uart:
|
if uart_support = "yes" generate
|
if uart_support = "yes" generate
|
enable_uart <= '1' when periph_access = '1' and data_addr_cpu(7 downto 4) = "1110" else '0';
|
enable_uart <= '1' when periph_access = '1' and address_cpu(7 downto 4) = "1110" else '0';
|
enable_uart_write <= enable_uart and periph_access_we;
|
enable_uart_write <= enable_uart and periph_access_we;
|
enable_uart_read <= enable_uart and not periph_access_we;
|
enable_uart_read <= enable_uart and not periph_access_we;
|
|
|
-- a simple UART
|
-- a simple UART
|
serial: entity work.uart
|
serial: entity work.uart
|
generic map (log_file => log_file)
|
generic map (log_file => log_file)
|
port map(
|
port map(
|
clk => clock,
|
clk => clock,
|
reset => reset,
|
reset => reset,
|
divisor => uart_divisor(11 downto 0),
|
divisor => uart_divisor(11 downto 0),
|
enable_read => enable_uart_read,
|
enable_read => enable_uart_read,
|
enable_write => enable_uart_write,
|
enable_write => enable_uart_write,
|
data_in => data_write_uart,
|
data_in => data_write_uart,
|
data_out => data_read_uart,
|
data_out => data_read_uart,
|
uart_read => uart_read,
|
uart_read => uart_read,
|
uart_write => uart_write,
|
uart_write => uart_write,
|
busy_write => uart_write_busy,
|
busy_write => uart_write_busy,
|
data_avail => uart_data_avail
|
data_avail => uart_data_avail
|
);
|
);
|
end generate;
|
end generate;
|
|
|
no_uart:
|
no_uart:
|
if uart_support = "no" generate
|
if uart_support = "no" generate
|
enable_uart <= '0';
|
enable_uart <= '0';
|
data_read_uart <= (others => '0');
|
data_read_uart <= (others => '0');
|
uart_write_busy <= '0';
|
uart_write_busy <= '0';
|
uart_data_avail <= '0';
|
uart_data_avail <= '0';
|
end generate;
|
end generate;
|
|
|
end arch;
|
end arch;
|
|
|
|
|
