library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use std.textio.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity tb is
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entity tb is
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generic(
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generic(
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address_width: integer := 16;
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address_width: integer := 16;
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memory_file : string := "code.txt";
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memory_file : string := "code.txt";
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log_file: string := "out.txt";
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log_file: string := "out.txt";
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uart_support : string := "yes"
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uart_support : string := "no"
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);
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);
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end tb;
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end tb;
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architecture tb of tb is
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architecture tb of tb is
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signal clock_in, reset, busy_cpu, stall_cpu, data, stall, stall_sig: std_logic := '0';
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signal clock_in, reset, stall_cpu, data, stall, stall_sig: std_logic := '0';
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signal uart_read, uart_write: std_logic;
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signal uart_read, uart_write: std_logic;
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signal boot_enable_n, ram_enable_n, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly: std_logic;
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signal boot_enable_n, ram_enable_n, irq_cpu, irq_ack_cpu, exception_cpu, data_access_cpu, ram_dly: std_logic;
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, inst_addr_cpu, inst_in_cpu, data_addr_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal address, data_read, data_write, data_read_boot, data_read_ram, irq_vector_cpu, address_cpu, data_in_cpu, data_out_cpu: std_logic_vector(31 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal ext_irq: std_logic_vector(7 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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signal data_we, data_w_n_ram, data_w_cpu: std_logic_vector(3 downto 0);
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begin
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begin
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process --25Mhz system clock
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process --25Mhz system clock
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begin
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begin
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clock_in <= not clock_in;
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clock_in <= not clock_in;
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wait for 20 ns;
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wait for 20 ns;
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clock_in <= not clock_in;
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clock_in <= not clock_in;
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wait for 20 ns;
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wait for 20 ns;
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end process;
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end process;
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process
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process
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begin
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begin
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stall <= not stall;
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stall <= not stall;
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wait for 123 ns;
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wait for 123 ns;
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stall <= not stall;
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stall <= not stall;
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wait for 123 ns;
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wait for 123 ns;
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end process;
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end process;
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reset <= '0', '1' after 5 ns, '0' after 500 ns;
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reset <= '0', '1' after 5 ns, '0' after 500 ns;
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stall_sig <= stall;
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stall_sig <= '0'; --stall;
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ext_irq <= x"00";
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ext_irq <= x"00";
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uart_read <= '1';
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uart_read <= '1';
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boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_cpu = '0') or reset = '1' else '1';
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boot_enable_n <= '0' when (address(31 downto 28) = "0000" and stall_cpu = '0') or reset = '1' else '1';
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ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_cpu = '0') or reset = '1' else '1';
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ram_enable_n <= '0' when (address(31 downto 28) = "0100" and stall_cpu = '0') or reset = '1' else '1';
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data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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data_read <= data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
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data_w_n_ram <= not data_we;
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data_w_n_ram <= not data_we;
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process(clock_in, reset)
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process(clock_in, reset)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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ram_dly <= '0';
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ram_dly <= '0';
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elsif clock_in'event and clock_in = '1' then
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elsif clock_in'event and clock_in = '1' then
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ram_dly <= not ram_enable_n;
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ram_dly <= not ram_enable_n;
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end if;
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end if;
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end process;
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end process;
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-- HF-RISC core
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-- HF-RISC core
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core: entity work.datapath
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core: entity work.datapath
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port map( clock => clock_in,
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port map( clock => clock_in,
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reset => reset,
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reset => reset,
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stall => stall_cpu,
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stall => stall_cpu,
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busy => busy_cpu,
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irq_vector => irq_vector_cpu,
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irq_vector => irq_vector_cpu,
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irq => irq_cpu,
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irq => irq_cpu,
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irq_ack => irq_ack_cpu,
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irq_ack => irq_ack_cpu,
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exception => exception_cpu,
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exception => exception_cpu,
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inst_addr => inst_addr_cpu,
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address => address_cpu,
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inst_in => inst_in_cpu,
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data_addr => data_addr_cpu,
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data_in => data_in_cpu,
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data_in => data_in_cpu,
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data_out => data_out_cpu,
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data_out => data_out_cpu,
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data_w => data_w_cpu,
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data_w => data_w_cpu,
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data_access => data_access_cpu
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data_access => data_access_cpu
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);
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);
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-- peripherals / busmux logic
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-- peripherals / busmux logic
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peripherals_busmux: entity work.busmux
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peripherals_busmux: entity work.busmux
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generic map(
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generic map(
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log_file => log_file,
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log_file => log_file,
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uart_support => uart_support
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uart_support => uart_support
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)
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)
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port map(
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port map(
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clock => clock_in,
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clock => clock_in,
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reset => reset,
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reset => reset,
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stall => stall_sig,
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stall => stall_sig,
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stall_cpu => stall_cpu,
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stall_cpu => stall_cpu,
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busy_cpu => busy_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_vector_cpu => irq_vector_cpu,
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irq_cpu => irq_cpu,
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irq_cpu => irq_cpu,
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irq_ack_cpu => irq_ack_cpu,
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irq_ack_cpu => irq_ack_cpu,
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exception_cpu => exception_cpu,
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exception_cpu => exception_cpu,
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inst_addr_cpu => inst_addr_cpu,
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address_cpu => address_cpu,
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inst_in_cpu => inst_in_cpu,
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data_addr_cpu => data_addr_cpu,
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data_in_cpu => data_in_cpu,
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data_in_cpu => data_in_cpu,
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data_out_cpu => data_out_cpu,
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data_out_cpu => data_out_cpu,
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data_w_cpu => data_w_cpu,
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data_w_cpu => data_w_cpu,
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data_access_cpu => data_access_cpu,
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data_access_cpu => data_access_cpu,
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addr_mem => address,
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addr_mem => address,
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data_read_mem => data_read,
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data_read_mem => data_read,
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data_write_mem => data_write,
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data_write_mem => data_write,
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data_we_mem => data_we,
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data_we_mem => data_we,
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extio_in => ext_irq,
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extio_in => ext_irq,
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extio_out => open,
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extio_out => open,
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uart_read => uart_read,
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uart_read => uart_read,
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uart_write => uart_write
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uart_write => uart_write
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);
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);
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-- boot ROM
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-- boot ROM
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boot0lb: entity work.boot_ram
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boot0lb: entity work.boot_ram
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generic map ( memory_file => "boot.txt",
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generic map ( memory_file => "boot.txt",
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data_width => 8,
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data_width => 8,
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address_width => 12,
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address_width => 12,
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bank => 0)
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bank => 0)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(11 downto 2),
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addr => address(11 downto 2),
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cs_n => boot_enable_n,
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cs_n => boot_enable_n,
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we_n => '1',
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we_n => '1',
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data_i => (others => '0'),
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data_i => (others => '0'),
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data_o => data_read_boot(7 downto 0)
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data_o => data_read_boot(7 downto 0)
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);
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);
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boot0ub: entity work.boot_ram
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boot0ub: entity work.boot_ram
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generic map ( memory_file => "boot.txt",
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generic map ( memory_file => "boot.txt",
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data_width => 8,
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data_width => 8,
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address_width => 12,
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address_width => 12,
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bank => 1)
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bank => 1)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(11 downto 2),
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addr => address(11 downto 2),
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cs_n => boot_enable_n,
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cs_n => boot_enable_n,
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we_n => '1',
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we_n => '1',
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data_i => (others => '0'),
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data_i => (others => '0'),
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data_o => data_read_boot(15 downto 8)
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data_o => data_read_boot(15 downto 8)
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);
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);
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boot1lb: entity work.boot_ram
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boot1lb: entity work.boot_ram
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generic map ( memory_file => "boot.txt",
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generic map ( memory_file => "boot.txt",
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data_width => 8,
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data_width => 8,
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address_width => 12,
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address_width => 12,
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bank => 2)
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bank => 2)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(11 downto 2),
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addr => address(11 downto 2),
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cs_n => boot_enable_n,
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cs_n => boot_enable_n,
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we_n => '1',
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we_n => '1',
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data_i => (others => '0'),
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data_i => (others => '0'),
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data_o => data_read_boot(23 downto 16)
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data_o => data_read_boot(23 downto 16)
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);
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);
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boot1ub: entity work.boot_ram
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boot1ub: entity work.boot_ram
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generic map ( memory_file => "boot.txt",
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generic map ( memory_file => "boot.txt",
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data_width => 8,
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data_width => 8,
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address_width => 12,
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address_width => 12,
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bank => 3)
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bank => 3)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(11 downto 2),
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addr => address(11 downto 2),
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cs_n => boot_enable_n,
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cs_n => boot_enable_n,
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we_n => '1',
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we_n => '1',
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data_i => (others => '0'),
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data_i => (others => '0'),
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data_o => data_read_boot(31 downto 24)
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data_o => data_read_boot(31 downto 24)
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);
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);
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-- RAM
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-- RAM
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memory0lb: entity work.bram
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memory0lb: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 0)
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bank => 0)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(0),
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we_n => data_w_n_ram(0),
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data_i => data_write(7 downto 0),
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data_i => data_write(7 downto 0),
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data_o => data_read_ram(7 downto 0)
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data_o => data_read_ram(7 downto 0)
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);
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);
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memory0ub: entity work.bram
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memory0ub: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 1)
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bank => 1)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(1),
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we_n => data_w_n_ram(1),
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data_i => data_write(15 downto 8),
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data_i => data_write(15 downto 8),
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data_o => data_read_ram(15 downto 8)
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data_o => data_read_ram(15 downto 8)
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);
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);
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memory1lb: entity work.bram
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memory1lb: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 2)
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bank => 2)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(2),
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we_n => data_w_n_ram(2),
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data_i => data_write(23 downto 16),
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data_i => data_write(23 downto 16),
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data_o => data_read_ram(23 downto 16)
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data_o => data_read_ram(23 downto 16)
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);
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);
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memory1ub: entity work.bram
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memory1ub: entity work.bram
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generic map ( memory_file => memory_file,
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generic map ( memory_file => memory_file,
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data_width => 8,
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data_width => 8,
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address_width => address_width,
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address_width => address_width,
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bank => 3)
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bank => 3)
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port map(
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port map(
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clk => clock_in,
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clk => clock_in,
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addr => address(address_width -1 downto 2),
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addr => address(address_width -1 downto 2),
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cs_n => ram_enable_n,
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cs_n => ram_enable_n,
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we_n => data_w_n_ram(3),
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we_n => data_w_n_ram(3),
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data_i => data_write(31 downto 24),
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data_i => data_write(31 downto 24),
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data_o => data_read_ram(31 downto 24)
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data_o => data_read_ram(31 downto 24)
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);
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);
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-- debug process
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-- debug process
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debug:
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debug:
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if uart_support = "no" generate
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if uart_support = "no" generate
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process(clock_in, data_addr_cpu)
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process(clock_in, address_cpu)
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file store_file : text open write_mode is "debug.txt";
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file store_file : text open write_mode is "debug.txt";
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variable hex_file_line : line;
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variable hex_file_line : line;
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variable c : character;
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variable c : character;
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variable index : natural;
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variable index : natural;
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variable line_length : natural := 0;
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variable line_length : natural := 0;
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begin
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begin
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if clock_in'event and clock_in = '1' then
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if clock_in'event and clock_in = '1' then
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if data_addr_cpu = x"f00000d0" and data = '0' then
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if address_cpu = x"f00000d0" and data = '0' then
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data <= '1';
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data <= '1';
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index := conv_integer(data_write(30 downto 24));
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index := conv_integer(data_write(30 downto 24));
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if index /= 10 then
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if index /= 10 then
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c := character'val(index);
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c := character'val(index);
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write(hex_file_line, c);
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write(hex_file_line, c);
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line_length := line_length + 1;
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line_length := line_length + 1;
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end if;
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end if;
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if index = 10 or line_length >= 72 then
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if index = 10 or line_length >= 72 then
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writeline(store_file, hex_file_line);
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writeline(store_file, hex_file_line);
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line_length := 0;
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line_length := 0;
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end if;
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end if;
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else
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else
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data <= '0';
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data <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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|
|
process(clock_in, reset, address)
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process(clock_in, reset, address)
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begin
|
begin
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if reset = '1' then
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if reset = '1' then
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elsif clock_in'event and clock_in = '0' then
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elsif clock_in'event and clock_in = '0' then
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assert address /= x"e0000000" report "end of simulation" severity failure;
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assert address /= x"e0000000" report "end of simulation" severity failure;
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assert (address < x"50000000") or (address >= x"f0000000") report "out of memory region" severity failure;
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assert (address < x"50000000") or (address >= x"f0000000") report "out of memory region" severity failure;
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assert address /= x"40000100" report "handling IRQ" severity warning;
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assert address /= x"40000100" report "handling IRQ" severity warning;
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end if;
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end if;
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end process;
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end process;
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|
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end tb;
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end tb;
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