#include <hf-risc.h>
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#include <hf-risc.h>
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volatile int32_t ccount=0, ccount2=0, cmpcount=0, cmp2count=0, irq0count=0, irq1count=0;
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volatile int32_t ccount=0, ccount2=0, cmpcount=0, cmp2count=0;
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/*
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/*
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ISRs - interrupt service routines
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ISRs - interrupt service routines
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*/
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*/
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void counter_handler(void){ // 10.48ms @ 25MHz
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void counter_handler(void){ // 10.48ms @ 25MHz
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uint32_t m;
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uint32_t m;
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ccount++;
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ccount++;
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m = IRQ_MASK; // read interrupt mask
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m = IRQ_MASK; // read interrupt mask
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m ^= (IRQ_COUNTER | IRQ_COUNTER_NOT); // toggle timer interrupt mask
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m ^= (IRQ_COUNTER | IRQ_COUNTER_NOT); // toggle timer interrupt mask
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IRQ_MASK = m; // write to irq mask register
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IRQ_MASK = m; // write to irq mask register
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}
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}
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void counter_handler2(void){ // 2.62ms @ 25MHz
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void counter_handler2(void){ // 2.62ms @ 25MHz
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uint32_t m;
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uint32_t m;
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ccount2++;
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ccount2++;
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m = IRQ_MASK; // read interrupt mask
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m = IRQ_MASK; // read interrupt mask
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m ^= (IRQ_COUNTER2 | IRQ_COUNTER2_NOT); // toggle timer interrupt mask
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m ^= (IRQ_COUNTER2 | IRQ_COUNTER2_NOT); // toggle timer interrupt mask
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IRQ_MASK = m; // write to irq mask register
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IRQ_MASK = m; // write to irq mask register
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}
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}
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void compare_handler(void){
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void compare_handler(void){
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uint32_t val;
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uint32_t val;
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cmpcount++;
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cmpcount++;
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val = COUNTER;
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val = COUNTER;
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val += (CPU_SPEED/1000) * 5; // 5 ms @ 25MHz
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val += (CPU_SPEED/1000) * 5; // 5 ms @ 25MHz
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COMPARE = val; // update compare reg, clear irq
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COMPARE = val; // update compare reg, clear irq
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}
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}
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void compare2_handler(void){
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void compare2_handler(void){
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uint32_t val;
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uint32_t val;
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cmp2count++;
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cmp2count++;
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val = COUNTER;
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val = COUNTER;
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val += (CPU_SPEED/1000) * 1; // 1 ms @ 25MHz
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val += (CPU_SPEED/1000) * 1; // 1 ms @ 25MHz
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COMPARE2 = val; // update compare2 reg, clear irq
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COMPARE2 = val; // update compare2 reg, clear irq
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}
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}
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void irq0_handler(void){
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irq0count++;
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}
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void irq1_handler(void){
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irq1count++;
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}
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int main(void){
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int main(void){
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// register ISRs
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// register ISRs
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interrupt_register(IRQ_COUNTER, counter_handler);
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interrupt_register(IRQ_COUNTER, counter_handler);
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interrupt_register(IRQ_COUNTER_NOT, counter_handler);
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interrupt_register(IRQ_COUNTER_NOT, counter_handler);
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interrupt_register(IRQ_COUNTER2, counter_handler2);
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interrupt_register(IRQ_COUNTER2, counter_handler2);
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interrupt_register(IRQ_COUNTER2_NOT, counter_handler2);
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interrupt_register(IRQ_COUNTER2_NOT, counter_handler2);
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interrupt_register(IRQ_COMPARE, compare_handler);
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interrupt_register(IRQ_COMPARE, compare_handler);
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interrupt_register(IRQ_COMPARE2, compare2_handler);
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interrupt_register(IRQ_COMPARE2, compare2_handler);
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interrupt_register(EXT_IRQ0, irq0_handler);
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interrupt_register(EXT_IRQ1, irq1_handler);
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// initialize compare registers, clear compare irqs
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// initialize compare registers, clear compare irqs
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COMPARE = COUNTER + (CPU_SPEED/1000) * 5;
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COMPARE = COUNTER + (CPU_SPEED/1000) * 5;
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COMPARE2 = COUNTER + (CPU_SPEED/1000) * 1;
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COMPARE2 = COUNTER + (CPU_SPEED/1000) * 1;
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// set interrupt mask (unmask peripheral interrupts)
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// set interrupt mask (unmask peripheral interrupts)
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IRQ_MASK = (IRQ_COUNTER | IRQ_COUNTER2 | IRQ_COMPARE | IRQ_COMPARE2 | EXT_IRQ0 | EXT_IRQ1);
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IRQ_MASK = (IRQ_COUNTER | IRQ_COUNTER2 | IRQ_COMPARE | IRQ_COMPARE2);
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// global interrupts enable
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// global interrupts enable
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IRQ_STATUS = 1;
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IRQ_STATUS = 1;
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ccount=0; ccount2=0; cmpcount=0; cmp2count=0; irq0count=0; irq1count=0;
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ccount=0; ccount2=0; cmpcount=0; cmp2count=0;
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for(;;){
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for(;;){
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printf("\ninterrupts -> counter18: %d counter16: %d compare: %d compare2: %d ext_irq0: %d ext_irq1: %d", ccount, ccount2, cmpcount, cmp2count, irq0count, irq1count);
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printf("\ninterrupts -> counter18: %d counter16: %d compare: %d compare2: %d", ccount, ccount2, cmpcount, cmp2count);
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}
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}
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}
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}
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