.text
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.text
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.align 2
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.align 2
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.global _entry
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.global _entry
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_entry:
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_entry:
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la a3, _bss_start
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la a3, _bss_start
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la a2, _end
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la a2, _end
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la gp, _gp
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la gp, _gp
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la sp, _stack
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la sp, _stack
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la tp, _end + 63
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la tp, _end + 63
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and tp, tp, -64
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and tp, tp, -64
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BSS_CLEAR:
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BSS_CLEAR:
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# clear the .bss
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# clear the .bss
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sw zero, 0(a3)
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sw zero, 0(a3)
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addi a3, a3, 4
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addi a3, a3, 4
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blt a3, a2, BSS_CLEAR
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blt a3, a2, BSS_CLEAR
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# configure IRQ_VECTOR
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# configure IRQ_VECTOR
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la s11, _isr
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la s11, _isr
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li s10, 0xf0000000
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li s10, 0xf0000000
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sw s11, 0(s10)
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sw s11, 0(s10)
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# jump to main
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# jump to main
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jal ra, main
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jal ra, main
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li s10, 0xe0000000 # this will interrupt the simulation (assertion)
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li s10, 0xe0000000 # this will interrupt the simulation (assertion)
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sw zero, 0(s10)
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sw zero, 0(s10)
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L1:
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L1:
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beq zero, zero, L1
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beq zero, zero, L1
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# interrupt / exception service routine
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# interrupt / exception service routine
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.org 0x100
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.org 0x100
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.global _isr
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.global _isr
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_isr:
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_isr:
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nop # this must be a NOP
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nop # this must be a NOP
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addi sp, sp, -68
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addi sp, sp, -68
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sw ra, 0(sp)
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sw ra, 0(sp)
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sw t0, 4(sp)
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sw t0, 4(sp)
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sw t1, 8(sp)
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sw t1, 8(sp)
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sw t2, 12(sp)
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sw t2, 12(sp)
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sw a0, 16(sp)
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sw a0, 16(sp)
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sw a1, 20(sp)
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sw a1, 20(sp)
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sw a2, 24(sp)
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sw a2, 24(sp)
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sw a3, 28(sp)
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sw a3, 28(sp)
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sw a4, 32(sp)
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sw a4, 32(sp)
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sw a5, 36(sp)
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sw a5, 36(sp)
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sw a6, 40(sp)
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sw a6, 40(sp)
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sw a7, 44(sp)
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sw a7, 44(sp)
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sw t3, 48(sp)
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sw t3, 48(sp)
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sw t4, 52(sp)
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sw t4, 52(sp)
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sw t5, 56(sp)
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sw t5, 56(sp)
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sw t6, 60(sp)
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sw t6, 60(sp)
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li s10, 0xf0000040 # read IRQ_EPC
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li s10, 0xf0000040 # read IRQ_EPC
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lw s10, 0(s10)
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lw s10, 0(s10)
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addi s10, s10, -4 # rollback, last opcode (at EPC) was not commited
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addi s10, s10, -4 # rollback, last opcode (at EPC) was not commited
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sw s10, 64(sp)
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sw s10, 64(sp)
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lui a1, 0xf0000
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lui a1, 0xf0000
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lw a0, 0x10(a1) # read IRQ_CAUSE
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lw a0, 0x10(a1) # read IRQ_CAUSE
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lw a2, 0x20(a1) # read IRQ_MASK
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lw a2, 0x20(a1) # read IRQ_MASK
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and a0, a0, a2 # pass CAUSE and MASK and the stack pointer to the C handler
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and a0, a0, a2 # pass CAUSE and MASK and the stack pointer to the C handler
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addi a1, sp, 0
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addi a1, sp, 0
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beq a0, zero, _exception # it's an exception, not an interrupt
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beq a0, zero, _exception # it's an exception, not an interrupt
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jal ra, interrupt_handler # jump to C handler
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jal ra, interrupt_handler # jump to C handler
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_restore:
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_restore:
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lw ra, 0(sp)
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lw ra, 0(sp)
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lw t0, 4(sp)
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lw t0, 4(sp)
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lw t1, 8(sp)
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lw t1, 8(sp)
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lw t2, 12(sp)
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lw t2, 12(sp)
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lw a0, 16(sp)
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lw a0, 16(sp)
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lw a1, 20(sp)
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lw a1, 20(sp)
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lw a2, 24(sp)
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lw a2, 24(sp)
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lw a3, 28(sp)
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lw a3, 28(sp)
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lw a4, 32(sp)
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lw a4, 32(sp)
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lw a5, 36(sp)
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lw a5, 36(sp)
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lw a6, 40(sp)
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lw a6, 40(sp)
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lw a7, 44(sp)
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lw a7, 44(sp)
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lw t3, 48(sp)
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lw t3, 48(sp)
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lw t4, 52(sp)
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lw t4, 52(sp)
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lw t5, 56(sp)
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lw t5, 56(sp)
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lw t6, 60(sp)
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lw t6, 60(sp)
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addi sp, sp, 68
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addi sp, sp, 68
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ori s11, zero, 0x1
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ori s11, zero, 0x1
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li s10, 0xf0000030
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li s10, 0xf0000030
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sw s11, 0(s10) # enable interrupts after a few cycles
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sw s11, 0(s10) # enable interrupts after a few cycles
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lw s10, -4(sp)
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lw s10, -4(sp)
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jalr zero, s10 # context restored, continue
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jalr zero, s10 # context restored, continue
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_exception:
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_exception:
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addi s10, s10, -4 # s10 is IRQ_EPC-4, actual EPC is IRQ_EPC-8
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addi s10, s10, -4 # s10 is IRQ_EPC-4, actual EPC is IRQ_EPC-8
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lw s11, 0(s10) # read opcode
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lw s11, 0(s10) # read opcode
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addi a0, s10, 0
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addi a0, s10, 0
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addi a1, s11, 0
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addi a1, s11, 0
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jal ra, exception_handler # TODO: set rd reg on some exceptions
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jal ra, exception_handler # TODO: set rd reg on some exceptions
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jal zero, _restore
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jal zero, _restore
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.global _interrupt_set
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.global _interrupt_set
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_interrupt_set:
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_interrupt_set:
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li a1, 0xf0000030
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li a1, 0xf0000030
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lw a2, 0(a1)
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lw a2, 0(a1)
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sw a0, 0(a1)
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sw a0, 0(a1)
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addi a0, a2, 0
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addi a0, a2, 0
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ret
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ret
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.global setjmp
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.global setjmp
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setjmp:
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setjmp:
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sw s0, 0(a0)
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sw s0, 0(a0)
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sw s1, 4(a0)
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sw s1, 4(a0)
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sw s2, 8(a0)
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sw s2, 8(a0)
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sw s3, 12(a0)
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sw s3, 12(a0)
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sw s4, 16(a0)
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sw s4, 16(a0)
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sw s5, 20(a0)
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sw s5, 20(a0)
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sw s6, 24(a0)
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sw s6, 24(a0)
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sw s7, 28(a0)
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sw s7, 28(a0)
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sw s8, 32(a0)
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sw s8, 32(a0)
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sw s9, 36(a0)
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sw s9, 36(a0)
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# sw gp, 40(a0)
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# sw gp, 40(a0)
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sw tp, 44(a0)
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sw tp, 44(a0)
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sw sp, 48(a0)
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sw sp, 48(a0)
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sw ra, 52(a0)
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sw ra, 52(a0)
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ori a0, zero, 0
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ori a0, zero, 0
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ret
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ret
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.global longjmp
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.global longjmp
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longjmp:
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longjmp:
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lw s0, 0(a0)
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lw s0, 0(a0)
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lw s1, 4(a0)
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lw s1, 4(a0)
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lw s2, 8(a0)
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lw s2, 8(a0)
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lw s3, 12(a0)
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lw s3, 12(a0)
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lw s4, 16(a0)
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lw s4, 16(a0)
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lw s5, 20(a0)
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lw s5, 20(a0)
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lw s6, 24(a0)
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lw s6, 24(a0)
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lw s7, 28(a0)
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lw s7, 28(a0)
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lw s8, 32(a0)
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lw s8, 32(a0)
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lw s9, 36(a0)
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lw s9, 36(a0)
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# lw gp, 40(a0)
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# lw gp, 40(a0)
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lw tp, 44(a0)
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lw tp, 44(a0)
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lw sp, 48(a0)
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lw sp, 48(a0)
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lw ra, 52(a0)
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lw ra, 52(a0)
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ori a0, a1, 0
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ori a0, a1, 0
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ret
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ret
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.global _restoreexec
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_restoreexec:
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lw s0, 0(a0)
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lw s1, 4(a0)
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lw s2, 8(a0)
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lw s3, 12(a0)
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lw s4, 16(a0)
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lw s5, 20(a0)
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lw s6, 24(a0)
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lw s7, 28(a0)
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lw s8, 32(a0)
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lw s9, 36(a0)
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# lw gp, 40(a0)
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lw tp, 44(a0)
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lw sp, 48(a0)
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lw ra, 52(a0)
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ori s11, zero, 0x1
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li s10, 0xf0000030
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ori a0, a1, 0
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sw s11, 0(s10) # enable interrupts
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ret
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No newline at end of file
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No newline at end of file
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