------------------------------------------------------------------
|
------------------------------------------------------------------
|
-- PROJECT: HiCoVec (highly configurable vector processor)
|
-- PROJECT: HiCoVec (highly configurable vector processor)
|
--
|
--
|
-- ENTITY: selectunit
|
-- ENTITY: selectunit
|
--
|
--
|
-- PURPOSE: selects one word out of a vector
|
-- PURPOSE: selects one word out of a vector
|
-- register
|
-- register
|
--
|
--
|
-- AUTHOR: harald manske, haraldmanske@gmx.de
|
-- AUTHOR: harald manske, haraldmanske@gmx.de
|
--
|
--
|
-- VERSION: 1.0
|
-- VERSION: 1.0
|
-----------------------------------------------------------------
|
-----------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
use work.cfg.all;
|
use work.cfg.all;
|
use work.datatypes.all;
|
use work.datatypes.all;
|
|
|
entity selectunit is
|
entity selectunit is
|
port (
|
port (
|
data_in : in vectordata_type;
|
data_in : in vectordata_type;
|
k_in: in std_logic_vector(31 downto 0);
|
k_in: in std_logic_vector(31 downto 0);
|
data_out: out std_logic_vector(31 downto 0)
|
data_out: out std_logic_vector(31 downto 0)
|
);
|
);
|
end selectunit;
|
end selectunit;
|
|
|
architecture rtl of selectunit is
|
architecture rtl of selectunit is
|
signal index: integer range 0 to k-1;
|
signal index: integer range 0 to k-1;
|
begin
|
begin
|
index <= conv_integer(k_in) when (k_in < k) else 0;
|
index <= conv_integer(k_in) when (k_in < k) else 0;
|
data_out <= data_in(index);
|
data_out <= data_in(index);
|
|
|
