-- High load test project. ***** TOP level file *****
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-- High load test project. ***** TOP level file *****
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-- Alexey Fedorov, 2014
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-- Alexey Fedorov, 2014
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-- email: FPGA@nerudo.com
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-- email: FPGA@nerudo.com
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--
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--
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-- It is intended for checking device
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-- It is intended for checking device
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-- for high consumption power.
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-- for high consumption power.
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-- Number of parameter gives possibility
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-- Number of parameter gives possibility
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-- to change number of used LC/DFF, DSP, RAM and I/O.
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-- to change number of used LC/DFF, DSP, RAM and I/O.
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--
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--
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-- It can operate at 200 MHz in Cyclone 5E FPGA
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-- It can operate at 200 MHz in Cyclone 5E FPGA
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--
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--
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-- 1 LC core is about 1500 LUT4/FF (with default parameters)
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-- 1 LC core is about 1500 LUT4/FF (with default parameters)
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-- 1 DSP core is 7 DSP 18*18.
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-- 1 DSP core is 7 DSP 18*18.
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-- Each LC core also demands 4*N RAM block (32 bits width)
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-- Each LC core also demands 4*N RAM block (32 bits width)
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--To maximize power consumption:
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--To maximize power consumption:
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--1) Find parameters for maximum FPGA resource usage
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--1) Find parameters for maximum FPGA resource usage
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--2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
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--2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
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--3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
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--3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
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--4) Connect maximal count of outputs. Be careful: They are switching simultaneously.
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--4) Connect maximal count of outputs. Be careful: They are switching simultaneously.
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--
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--
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-- **** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****
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-- **** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity high_load is
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entity high_load is
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generic (
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generic (
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NUM_IN : positive := 3*14; -- Input pins
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NUM_IN : positive := 3*14; -- Input pins
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NUM_OUT : positive := 1; -- Output pins
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NUM_OUT : positive := 1; -- Output pins
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NUM_LC : positive := 16; -- Number of LC cores
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NUM_LC : positive := 16; -- Number of LC cores
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LC_RECURSION : positive := 1; -- 1 = no recursion
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NUM_DSP : positive := 9; -- Number of DSP cores
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NUM_DSP : positive := 9; -- Number of DSP cores
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RAM_DEPTH_LOG2 : integer range 4 to 30 := 10 -- RAM depth
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RAM_DEPTH_LOG2 : integer range 4 to 30 := 10 -- RAM depth
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);
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);
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port
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port
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(
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(
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-- Input ports
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-- Input ports
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clk : in std_logic;
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clk : in std_logic;
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inputs: in std_logic_vector(NUM_IN-1 downto 0);
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inputs: in std_logic_vector(NUM_IN-1 downto 0);
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-- Output ports
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-- Output ports
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dataout: out std_logic_vector(NUM_OUT-1 downto 0)
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dataout: out std_logic_vector(NUM_OUT-1 downto 0)
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);
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);
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end high_load;
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end high_load;
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architecture rtl of high_load is
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architecture rtl of high_load is
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--component aes_test_wrap is
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--component aes_test_wrap is
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--port(
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--port(
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-- clk : in std_logic;
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-- clk : in std_logic;
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-- datain: in std_logic_vector(127 downto 0);
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-- datain: in std_logic_vector(127 downto 0);
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-- key : in std_logic_vector(127 downto 0);
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-- key : in std_logic_vector(127 downto 0);
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-- dataout: out std_logic_vector(127 downto 0)
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-- dataout: out std_logic_vector(127 downto 0)
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-- );
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-- );
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--end component;
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--end component;
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component lc_use is
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component lc_use is
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generic (
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generic (
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RECURSION_IDX : positive := 1; -- 1 = stop recursion
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DATA_WIDTH : positive := 128;
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DATA_WIDTH : positive := 128;
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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NUM_ROWS: positive := 6; -- Input pins
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NUM_ROWS: positive := 6; -- Input pins
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ADD_PIPL_FF : boolean := false
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ADD_PIPL_FF : boolean := false
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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);
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end component;
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end component;
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component dsp_use is
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component dsp_use is
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generic (
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generic (
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DATA_WIDTH : positive := 16
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DATA_WIDTH : positive := 16
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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datain: in std_logic_vector(DATA_WIDTH-1 downto 0);
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datain: in std_logic_vector(DATA_WIDTH-1 downto 0);
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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);
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end component;
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end component;
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component ram_buf IS
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component ram_buf IS
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generic (
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generic (
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DATA_WIDTH: positive := 12;
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DATA_WIDTH: positive := 12;
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DEPTH_LOG2: positive := 10
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DEPTH_LOG2: positive := 10
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);
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);
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port(
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port(
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clk : in std_logic; -- input data clock
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clk : in std_logic; -- input data clock
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-- ena : in std_logic; -- input data enable
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-- ena : in std_logic; -- input data enable
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din : in std_logic_vector(DATA_WIDTH-1 downto 0);
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din : in std_logic_vector(DATA_WIDTH-1 downto 0);
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delay : in std_logic_vector(DEPTH_LOG2-1 downto 0);
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delay : in std_logic_vector(DEPTH_LOG2-1 downto 0);
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dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
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dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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);
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END component;
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END component;
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constant DSP_WIDTH : integer := 15; -- Data width of DSP multipliers
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constant DSP_WIDTH : integer := 15; -- Data width of DSP multipliers
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constant LC_W : integer := 128*NUM_LC;
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constant LC_W : integer := 128*NUM_LC;
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constant DSP_W : integer := DSP_WIDTH*NUM_DSP;
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constant DSP_W : integer := DSP_WIDTH*NUM_DSP;
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--constant key : bit_vector(127 downto 0) := X"2BAC93F18E4797830BD476554BBE27A5";
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--constant key : bit_vector(127 downto 0) := X"2BAC93F18E4797830BD476554BBE27A5";
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signal lc_in, lc_out, ram_in, ram_out : std_logic_vector(LC_W-1 downto 0);
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signal lc_in, lc_out, ram_in, ram_out : std_logic_vector(LC_W-1 downto 0);
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signal dsp_in, dsp_out : std_logic_vector(DSP_W-1 downto 0);
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signal dsp_in, dsp_out : std_logic_vector(DSP_W-1 downto 0);
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signal xor_result : std_logic;
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signal xor_result : std_logic;
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procedure assign_bus(
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procedure assign_bus(
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signal inp : in std_logic_vector;
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signal inp : in std_logic_vector;
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signal outp : out std_logic_vector) is
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signal outp : out std_logic_vector) is
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constant IN_W : integer := inp'length(1);
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constant IN_W : integer := inp'length(1);
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constant OUT_W: integer := outp'length(1);
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constant OUT_W: integer := outp'length(1);
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begin
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begin
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for i in 1 to OUT_W/IN_W loop
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for i in 1 to OUT_W/IN_W loop
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if i = 1 then
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if i = 1 then
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outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp;
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outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp;
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else
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else
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outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp xor to_stdlogicvector(to_bitvector(inp) rol (i-1));
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outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp xor to_stdlogicvector(to_bitvector(inp) rol (i-1));
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end if;
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end if;
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end loop;
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end loop;
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if OUT_W mod IN_W > 0 then
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if OUT_W mod IN_W > 0 then
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outp(OUT_W-1 downto (OUT_W/IN_W)*IN_W) <= inp(OUT_W mod IN_W - 1 downto 0);
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outp(OUT_W-1 downto (OUT_W/IN_W)*IN_W) <= inp(OUT_W mod IN_W - 1 downto 0);
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end if;
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end if;
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end procedure;
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end procedure;
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procedure xorbus(
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procedure xorbus(
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signal inp : in std_logic_vector;
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signal inp : in std_logic_vector;
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signal outp : out std_logic
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signal outp : out std_logic
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) is
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) is
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variable tmp : std_logic := '0';
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variable tmp : std_logic := '0';
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begin
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begin
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for i in inp'range loop
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for i in inp'range loop
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tmp := tmp xor inp(i);
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tmp := tmp xor inp(i);
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end loop;
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end loop;
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outp <= tmp;
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outp <= tmp;
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end procedure;
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end procedure;
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procedure resultbus(
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procedure resultbus(
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signal inp : in std_logic_vector;
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signal inp : in std_logic_vector;
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signal outp : out std_logic
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signal outp : out std_logic
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) is
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) is
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variable tmp : integer := 0;
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variable tmp : integer := 0;
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begin
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begin
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for i in inp'range loop
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for i in inp'range loop
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if inp(i) = '1' then
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if inp(i) = '1' then
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tmp := tmp + 1;
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tmp := tmp + 1;
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end if;
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end if;
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end loop;
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end loop;
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if tmp >= inp'length(1) then
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if tmp >= inp'length(1) then
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outp <= '1';
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outp <= '1';
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else
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else
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outp <= '0';
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outp <= '0';
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end if;
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end if;
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end procedure;
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end procedure;
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begin
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begin
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assert lc_in'length(1) < dsp_in'length(1) report "Implementing Input => DSP => RAM => LC => Output" severity warning;
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assert lc_in'length(1) < dsp_in'length(1) report "Implementing Input => DSP => RAM => LC => Output" severity warning;
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assert lc_in'length(1) >= dsp_in'length(1) report "Implementing Input => LC => RAM => DSP => Output" severity warning;
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assert lc_in'length(1) >= dsp_in'length(1) report "Implementing Input => LC => RAM => DSP => Output" severity warning;
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process(clk) --inputs, lc_in, lc_out, ram_in, ram_out, dsp_in, dsp_out, xor_result)
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process(clk) --inputs, lc_in, lc_out, ram_in, ram_out, dsp_in, dsp_out, xor_result)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if(lc_in'length(1) < dsp_in'length(1)) then
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if(lc_in'length(1) < dsp_in'length(1)) then
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assign_bus(inputs, lc_in); -- Input => LC => RAM => DSP => Output
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assign_bus(inputs, lc_in); -- Input => LC => RAM => DSP => Output
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assign_bus(lc_out, ram_in);
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assign_bus(lc_out, ram_in);
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assign_bus(ram_out, dsp_in);
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assign_bus(ram_out, dsp_in);
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-- resultbus(dsp_out, xor_result);
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-- resultbus(dsp_out, xor_result);
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xorbus(dsp_out, xor_result);
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xorbus(dsp_out, xor_result);
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dataout <= (others => xor_result);
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dataout <= (others => xor_result);
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else
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else
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assign_bus(inputs, dsp_in); -- Input => DSP => RAM => LC => Output
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assign_bus(inputs, dsp_in); -- Input => DSP => RAM => LC => Output
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assign_bus(dsp_out, ram_in);
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assign_bus(dsp_out, ram_in);
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assign_bus(ram_out, lc_in);
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assign_bus(ram_out, lc_in);
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-- resultbus(lc_out, xor_result);
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-- resultbus(lc_out, xor_result);
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xorbus(lc_out, xor_result);
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xorbus(lc_out, xor_result);
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dataout <= (others => xor_result);
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dataout <= (others => xor_result);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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LC_GEN: for i in 0 to NUM_LC-1 generate
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LC_GEN: for i in 0 to NUM_LC-1 generate
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-- aes_i : aes_test_wrap
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-- aes_i : aes_test_wrap
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-- port map(
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-- port map(
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-- clk => clk,
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-- clk => clk,
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-- datain => aes_in(128*i+127 downto 128*i),
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-- datain => aes_in(128*i+127 downto 128*i),
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-- key => to_stdlogicvector(key rol i),
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-- key => to_stdlogicvector(key rol i),
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-- dataout=> aes_out(128*i+127 downto 128*i)
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-- dataout=> aes_out(128*i+127 downto 128*i)
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-- );
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-- );
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lc_i: lc_use
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lc_i: lc_use
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generic map (
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generic map (
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RECURSION_IDX => LC_RECURSION,
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DATA_WIDTH => 128,
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DATA_WIDTH => 128,
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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NUM_ROWS => 6, -- Input pins
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NUM_ROWS => 6, -- Input pins
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ADD_PIPL_FF => true
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ADD_PIPL_FF => true
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)
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)
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port map
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port map
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(
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(
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clk => clk,
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clk => clk,
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inputs => lc_in(128*i+127 downto 128*i),
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inputs => lc_in(128*i+127 downto 128*i),
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dataout=> lc_out(128*i+127 downto 128*i)
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dataout=> lc_out(128*i+127 downto 128*i)
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);
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);
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end generate;
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end generate;
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DSP_GEN: for i in 0 to NUM_DSP-1 generate
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DSP_GEN: for i in 0 to NUM_DSP-1 generate
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dsp_i : dsp_use
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dsp_i : dsp_use
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generic map(
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generic map(
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DATA_WIDTH => DSP_WIDTH)
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DATA_WIDTH => DSP_WIDTH)
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port map
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port map
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(
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(
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clk => clk,
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clk => clk,
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datain => dsp_in(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i),
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datain => dsp_in(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i),
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dataout => dsp_out(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i)
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dataout => dsp_out(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i)
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);
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);
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end generate;
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end generate;
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RAM_GEN: for i in 0 to NUM_LC-1 generate
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RAM_GEN: for i in 0 to NUM_LC-1 generate
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ram_i: ram_buf
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ram_i: ram_buf
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generic map(
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generic map(
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DATA_WIDTH => 128,
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DATA_WIDTH => 128,
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DEPTH_LOG2 => RAM_DEPTH_LOG2
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DEPTH_LOG2 => RAM_DEPTH_LOG2
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)
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)
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port map(
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port map(
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clk => clk,
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clk => clk,
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din => ram_in(128*i+127 downto 128*i),
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din => ram_in(128*i+127 downto 128*i),
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delay => std_logic_vector(to_unsigned(2**RAM_DEPTH_LOG2-10, RAM_DEPTH_LOG2)),
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delay => std_logic_vector(to_unsigned(2**RAM_DEPTH_LOG2-10, RAM_DEPTH_LOG2)),
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dout => ram_out(128*i+127 downto 128*i)
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dout => ram_out(128*i+127 downto 128*i)
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);
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);
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end generate;
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end generate;
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end rtl;
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end rtl;
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