-- High load test project.
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-- High load test project.
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-- Alexey Fedorov, 2014
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-- Alexey Fedorov, 2014
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-- email: FPGA@nerudo.com
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-- email: FPGA@nerudo.com
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--
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--
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-- It implements 256 LUT/DFFs per one row (NUM_ROWS parameter)
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-- It implements 256 LUT/DFFs per one row (NUM_ROWS parameter)
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-- with default other parameters
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-- with default other parameters
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity lc_use is
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entity lc_use is
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generic (
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generic (
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RECURSION_IDX : positive := 1; -- 1 = stop recursion
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DATA_WIDTH : positive := 128;
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DATA_WIDTH : positive := 128;
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
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NUM_ROWS: positive := 6; -- Input pins
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NUM_ROWS: positive := 6; -- Input pins
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ADD_PIPL_FF : boolean := false
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ADD_PIPL_FF : boolean := false
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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);
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end lc_use;
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end lc_use;
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architecture rtl of lc_use is
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architecture rtl of lc_use is
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type TArr is array (natural range <>) of unsigned(127 downto 0);
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type TArr is array (natural range <>) of unsigned(127 downto 0);
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signal arr : TArr(0 to 3*NUM_ROWS) := (others => (others => '0'));
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signal arr : TArr(0 to 3*NUM_ROWS) := (others => (others => '0'));
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signal dataout_i: std_logic_vector(DATA_WIDTH-1 downto 0);
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begin
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begin
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assert DATA_WIDTH mod ARITH_SIZE = 0 report "ARITH_SIZE should be divider of DATA_WIDTH" severity error;
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assert DATA_WIDTH mod ARITH_SIZE = 0 report "ARITH_SIZE should be divider of DATA_WIDTH" severity error;
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process(clk)
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process(clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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arr(0)(DATA_WIDTH-1 downto 0) <= unsigned(inputs);
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arr(0)(DATA_WIDTH-1 downto 0) <= unsigned(inputs);
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for i in 0 to NUM_ROWS-1 loop
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for i in 0 to NUM_ROWS-1 loop
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arr(3*i+1) <= arr(3*i) xor (arr(3*i) rol 1) xor (arr(3*i) rol 2) xor (arr(3*i) rol 3);
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arr(3*i+1) <= arr(3*i) xor (arr(3*i) rol 1) xor (arr(3*i) rol 2) xor (arr(3*i) rol 3);
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for j in 0 to DATA_WIDTH/ARITH_SIZE-1 loop
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for j in 0 to DATA_WIDTH/ARITH_SIZE-1 loop
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arr(3*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
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arr(3*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
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arr(3*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
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arr(3*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
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arr(3*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
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arr(3*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
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end loop;
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end loop;
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if ADD_PIPL_FF then
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if ADD_PIPL_FF then
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arr(3*i+3) <= arr(3*i+2);
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arr(3*i+3) <= arr(3*i+2);
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end if;
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end if;
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end loop;
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end loop;
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dataout <= std_logic_vector(arr(3*NUM_ROWS));
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dataout_i <= std_logic_vector(arr(3*NUM_ROWS));
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end if;
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end if;
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end process;
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end process;
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no_ff_gen: if not ADD_PIPL_FF generate
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no_ff_gen: if not ADD_PIPL_FF generate
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ff_loop_gen: for i in 0 to NUM_ROWS-1 generate
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ff_loop_gen: for i in 0 to NUM_ROWS-1 generate
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arr(3*i+3) <= arr(3*i+2);
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arr(3*i+3) <= arr(3*i+2);
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end generate;
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end generate;
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end generate;
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end generate;
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gen_rec1: if RECURSION_IDX = 1 generate
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dataout <= dataout_i;
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end generate;
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gen_recN: if RECURSION_IDX > 1 generate
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lc_i: entity work.lc_use
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generic map (
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RECURSION_IDX => RECURSION_IDX-1,
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DATA_WIDTH => 128,
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ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
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NUM_ROWS => 6, -- Input pins
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ADD_PIPL_FF => true
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)
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port map
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(
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clk => clk,
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inputs => dataout_i,
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dataout=> dataout
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);
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end generate;
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end rtl;
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end rtl;
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