HyperMTA Processor Specifications
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HyperMTA Processor Specifications
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This is only a preliminary release and it is not complete.
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This is only a preliminary release and it is not complete.
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#######################################################################
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#######################################################################
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#######################################################################
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#######################################################################
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User/System Access
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User/System Access
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Registers:
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Registers:
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R0-R31: General Purpose Integer
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R0-R31: General Purpose Integer
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F0-F31: Floating Point Registers
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F0-F31: Floating Point Registers
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C0(F0,F1)-C15(F30,F31): Complex Floating Point Registers
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C0(F0,F1)-C15(F30,F31): Complex Floating Point Registers
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Instruction Format and Next Instruction Data Placement:
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Instruction Format and Next Instruction Data Placement:
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| 42 Bits(I) | 42 Bits(I) | 42 Bits(I) | 2 Bits(11) |
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| 42 Bits(I) | 42 Bits(I) | 42 Bits(I) | 2 Bits(11) |
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| 64 Bits(D) | 20 Bits(D) | 42 Bits(I) | 2 Bits(01) |
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| 64 Bits(D) | 20 Bits(D) | 42 Bits(I) | 2 Bits(01) |
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NID0(I/F) NID1(I)
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NID0(I/F) NID1(I)
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| 42 Bits(I) | 42 Bits(I) | 42 Bits(D) | 2 Bits(10) |
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| 42 Bits(I) | 42 Bits(I) | 42 Bits(D) | 2 Bits(10) |
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NID0(I)
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NID0(I)
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| 126 Bits(D) | 2 Bits(00) | (Complex)
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| 126 Bits(D) | 2 Bits(00) | (Complex)
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NID0(C)
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NID0(C)
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// 63 Bits of each float least significat bit is zeroed or oneed by instruction
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// 63 Bits of each float least significat bit is zeroed or oneed by instruction
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Next Instruction Data:
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Next Instruction Data:
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Inlined data stored within the next instruction. Nothing else to say except
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Inlined data stored within the next instruction. Nothing else to say except
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it is one of the ways in which we hide memory latency.
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it is one of the ways in which we hide memory latency.
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Internal VLIW Branching:
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Internal VLIW Branching:
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This is another way to hide latency.
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This is another way to hide latency.
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The following to reduce branch misprediction penalties since it'll be more
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The following to reduce branch misprediction penalties since it'll be more
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costly in this system:
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costly in this system:
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| Conditional Branch | ALU OP | ALU OP |
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| Conditional Branch | ALU OP | ALU OP |
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If true the instruction will execute:
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If true the instruction will execute:
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| ALU | ALU | IGNORE THIS ALU OP |
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| ALU | ALU | IGNORE THIS ALU OP |
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else
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else
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| IGNORE THIS | ALU | ALU OP |
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| IGNORE THIS | ALU | ALU OP |
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Both of those were the same instruction. The Branch instruction contains
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Both of those were the same instruction. The Branch instruction contains
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a mask of which molecules to execute of the next instruction. In a standard
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a mask of which molecules to execute of the next instruction. In a standard
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pipelined system all three can be executed and in the write back stage the
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pipelined system all three can be executed and in the write back stage the
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correct molecules will be writen back. This can eliminate small loops.
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correct molecules will be writen back. This can eliminate small loops.
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Then a special return instruction will return the execution back to normal
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Then a special return instruction will return the execution back to normal
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executing all instructions. As in the example it is possible to have
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executing all instructions. As in the example it is possible to have
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shared instructions which will be executed either way.
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shared instructions which will be executed either way.
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ISA:
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ISA:
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Arithmetic(64 bit):
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Arithmetic(64 bit):
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ADD reg,reg,reg/imm
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ADD reg,reg,reg/imm
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SUB reg,reg,reg/imm
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SUB reg,reg,reg/imm
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MUL reg,reg,reg/imm
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MUL reg,reg,reg/imm
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MULU reg,reg,reg/imm
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MULU reg,reg,reg/imm
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DIV reg,reg,reg/imm
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DIV reg,reg,reg/imm
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DIVU reg,reg,reg/imm
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DIVU reg,reg,reg/imm
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MOD reg,reg,reg/imm
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MOD reg,reg,reg/imm
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MODU reg,reg,reg/imm
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MODU reg,reg,reg/imm
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LMUL reg,reg,reg,reg/imm // Long multiply
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LMUL reg,reg,reg,reg/imm // Long multiply
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LMULU reg,reg,reg,reg/imm // Long multiply unsigned
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LMULU reg,reg,reg,reg/imm // Long multiply unsigned
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Logic(64 bit):
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Logic(64 bit):
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OR reg,reg,reg/imm
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OR reg,reg,reg/imm
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AND reg,reg,reg/imm
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AND reg,reg,reg/imm
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XOR reg,reg,reg/imm
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XOR reg,reg,reg/imm
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NOT reg,reg
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NOT reg,reg
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SHL reg,reg,reg/imm
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SHL reg,reg,reg/imm
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SHR reg,reg,reg/imm
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SHR reg,reg,reg/imm
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ROL reg,reg,reg/imm
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ROL reg,reg,reg/imm
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ROR reg,reg,reg/imm
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ROR reg,reg,reg/imm
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PCNT reg,reg
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PCNT reg,reg
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PCNTZ reg,reg
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PCNTZ reg,reg
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PCNTC reg,reg
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PCNTC reg,reg
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CHG reg,reg
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CHG reg,reg
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SB reg,imm // Set Bit
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SB reg,imm // Set Bit
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CB reg,imm // Clear Bit
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CB reg,imm // Clear Bit
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TB reg,imm // Toggle Bit
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TB reg,imm // Toggle Bit
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Floating Point(64 Bit):
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Floating Point(64 Bit):
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FADD reg,reg,reg
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FADD reg,reg,reg
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FSUB reg,reg,reg
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FSUB reg,reg,reg
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FMUL reg,reg,reg
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FMUL reg,reg,reg
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FDIV reg,reg,reg
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FDIV reg,reg,reg
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FMOD reg,reg,reg
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FMOD reg,reg,reg
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FABS reg,reg
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FABS reg,reg
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FNEG reg,reg // Make Negative
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FNEG reg,reg // Make Negative
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FPOS reg,reg // Make Positive
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FPOS reg,reg // Make Positive
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FTSIGN reg,reg // Toggle Sign
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FTSIGN reg,reg // Toggle Sign
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FSQ reg,reg
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FSQ reg,reg
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FCMP reg,reg
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FCMP reg,reg
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FRND reg // Random Generator
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FRND reg // Random Generator
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FPI reg // Load PI
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FPI reg // Load PI
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FE reg // Load E
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FE reg // Load E
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FZERO reg // Load ZERO
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FZERO reg // Load ZERO
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FONE reg // Load ONE
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FONE reg // Load ONE
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FFLOOR reg,reg
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FFLOOR reg,reg
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FCEIL reg,reg
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FCEIL reg,reg
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FINV reg,reg // 1/reg
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FINV reg,reg // 1/reg
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Complex(128 Bit):
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Complex(128 Bit):
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CADD reg,reg,reg
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CADD reg,reg,reg
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CSUB reg,reg,reg
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CSUB reg,reg,reg
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CMUL reg,reg,reg
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CMUL reg,reg,reg
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CDIV reg,reg,reg
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CDIV reg,reg,reg
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CMOD reg,reg,reg // Do we really need this? I don't think so.
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CMOD reg,reg,reg // Do we really need this? I don't think so.
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CSQ reg,reg
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CSQ reg,reg
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CCMP reg,reg // ?
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CCMP reg,reg // ?
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CI reg // Load I
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CI reg // Load I
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Branch: // Avoid if possible user internal VLIW branching
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Branch: // Avoid if possible user internal VLIW branching
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JMP rel
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JMP rel
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JMP reg
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JMP reg
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JMP{condition} rel
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JMP{condition} rel
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JMP{condition} reg
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JMP{condition} reg
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CALL rel
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CALL rel
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CALL reg
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CALL reg
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CALL{condition} rel
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CALL{condition} rel
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CALL{condition} reg
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CALL{condition} reg
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CALL [reg+8*cccc]
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CALL [reg+8*cccc]
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CALL{condition} [reg+8*cccc]
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CALL{condition} [reg+8*cccc]
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RETURN
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RETURN
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RETURN{condition}
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RETURN{condition}
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Internal VLIW Branching:
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Internal VLIW Branching:
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// Selects to execute certain molecules of each atom until a return is reached
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// Selects to execute certain molecules of each atom until a return is reached
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// This is another way to hide memory latency
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// This is another way to hide memory latency
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IVB{condition} moleculemask(0,1,2, or any combination)
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IVB{condition} moleculemask(0,1,2, or any combination)
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IVRET
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IVRET
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Interupt:
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Interupt:
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THROW reg/imm
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THROW reg/imm
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RTI // Return Interupt
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RTI // Return Interupt
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Data Movement:
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Data Movement:
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MOV reg,reg // Move
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MOV reg,reg // Move
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MOVS reg,sreg // Move Special
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MOVS reg,sreg // Move Special
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MOVS sreg,reg
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MOVS sreg,reg
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PREFETCH // Data Prefetch
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PREFETCH // Data Prefetch
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PREFETCHI // Instruction Prefetch
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PREFETCHI // Instruction Prefetch
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LOADB(U)
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LOADB(U)
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LOADW(U)
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LOADW(U)
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LOADD(U)
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LOADD(U)
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LOADQ(U)
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LOADQ(U)
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STOREB
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STOREB
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STOREW
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STOREW
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STORED
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STORED
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STOREQ
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STOREQ
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LOADF // Load/Store Float
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LOADF // Load/Store Float
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STOREF
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STOREF
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LOADC // Load/Store Complex
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LOADC // Load/Store Complex
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STOREC
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STOREC
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LOADNID // Load from Next Instruction Data
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LOADNID // Load from Next Instruction Data
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LOADFNID // Load Float from Next Instruction Data
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LOADFNID // Load Float from Next Instruction Data
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LOADCNID // Load Complex from Next Instruction Data
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LOADCNID // Load Complex from Next Instruction Data
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EXTRACT reg(dest),reg(src),imm(start),imm(stop)
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EXTRACT reg(dest),reg(src),imm(start),imm(stop)
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DEPOSITE reg(dest),reg(src),reg(srcb),imm(start),imm(stop)
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DEPOSITE reg(dest),reg(src),reg(srcb),imm(start),imm(stop)
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System:
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System:
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TLBR reg(threadid),reg(tlbvalueh),reg(tlbvaluel)
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TLBR reg(threadid),reg(tlbvalueh),reg(tlbvaluel)
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TLBW reg(threadid),reg(tlbvalueh),reg(tlbvaluel)
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TLBW reg(threadid),reg(tlbvalueh),reg(tlbvaluel)
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Interupts: -- Avoid this unless absolutely nessicary
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Interupts: -- Avoid this unless absolutely nessicary
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THROW reg/imm(vector) // Throw Exception
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THROW reg/imm(vector) // Throw Exception
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RETI // Return from Interupt
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RETI // Return from Interupt
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System:
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System:
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IFENCE // Instruction Fence
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IFENCE // Instruction Fence
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DFENCE // Data Fence
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DFENCE // Data Fence
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REGISTER reg(threadptr),imm(interupt vector) // Registers an interupt
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REGISTER reg(threadptr),imm(interupt vector) // Registers an interupt
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SYSCALL // Syscall (Pauses Current Stream/Flags for Service)
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SYSCALL // Syscall (Pauses Current Stream/Flags for Service)
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Process Management: // Dispatched through MP Bus (8 Threads = 1 Process)
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Process Management: // Dispatched through MP Bus (8 Threads = 1 Process)
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PROCESS.LOAD reg(addrptr),reg(processorid:processid)
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PROCESS.LOAD reg(addrptr),reg(processorid:processid)
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PROCESS.STORE reg(addrptr),reg(processorid:processid)
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PROCESS.STORE reg(addrptr),reg(processorid:processid)
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PROCESS.START reg(processorid:processid)
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PROCESS.START reg(processorid:processid)
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PROCESS.STOP reg(processorid:processid)
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PROCESS.STOP reg(processorid:processid)
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Thread Management: // Dispatched through MP Bus
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Thread Management: // Dispatched through MP Bus
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THREAD.LOAD reg(addrptr),reg(processorid:threadid) // Loads a threads state
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THREAD.LOAD reg(addrptr),reg(processorid:threadid) // Loads a threads state
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THREAD.STORE reg(addrptr),reg(processorid:threadid) // Saves a threads state
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THREAD.STORE reg(addrptr),reg(processorid:threadid) // Saves a threads state
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THREAD.START reg(processorid:threadid) // Continues execution of a thread
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THREAD.START reg(processorid:threadid) // Continues execution of a thread
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THREAD.STOP reg(processorid:threadid) // Stops execution of a thread
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THREAD.STOP reg(processorid:threadid) // Stops execution of a thread
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BREAK // Debugger Support
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BREAK // Debugger Support
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Processor Management: // Dispatched through MP Bus
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Processor Management: // Dispatched through MP Bus
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PROCESSOR.START reg(processorid) // Start the processor
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PROCESSOR.START reg(processorid) // Start the processor
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PROCESSOR.STOP reg(processorid) // Stop the processor
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PROCESSOR.STOP reg(processorid) // Stop the processor
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PROCESSOR.PAUSE reg(processorid) // Pause a processor and all it's streams
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PROCESSOR.PAUSE reg(processorid) // Pause a processor and all it's streams
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PROCESSOR.CONTINUE reg(processorid) // Resume a processor from pause
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PROCESSOR.CONTINUE reg(processorid) // Resume a processor from pause
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PROCESSOR.RESET reg(processorid) // Restart a processor
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PROCESSOR.RESET reg(processorid) // Restart a processor
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PROCESSOR.PING reg(processorid),reg(result/hop count) // Ping's a processor
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PROCESSOR.PING reg(processorid),reg(result/hop count) // Ping's a processor
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// result is number of hops to processor or 0 for nonexistant
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// result is number of hops to processor or 0 for nonexistant
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Processor IDs:
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Processor IDs:
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0000: Startup
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0000: Startup
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0001: Master Processor (OS Only)
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0001: Master Processor (OS Only)
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0002-FFFE: Slave Processors
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0002-FFFE: Slave Processors
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FFFF: Broadcast ID
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FFFF: Broadcast ID
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Routing:
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Routing:
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-----------1-------------2---------------3------------
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-----------1-------------2---------------3------------
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-----------4-------------5 NO CONNECTION 6------------
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-----------4-------------5 NO CONNECTION 6------------
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-----------7-------------8---------------9------------
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-----------7-------------8---------------9------------
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Each router will automatically keep track of processor id's and their routing keys
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Each router will automatically keep track of processor id's and their routing keys
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and each router will try to route to a specified processor using the best way possible
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and each router will try to route to a specified processor using the best way possible
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When a processor is assigned a processor id it automatically tells the router its
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When a processor is assigned a processor id it automatically tells the router its
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id and the router from then on builds routing key tables as data transfers occur.
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id and the router from then on builds routing key tables as data transfers occur.
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Routers also buffer memory transfers and cache for their own memory banks.
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Routers also buffer memory transfers and cache for their own memory banks.
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The routing processors must be capable of sustaining 1 memory read/write to
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The routing processors must be capable of sustaining 1 memory read/write to
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each processor every clock cycle. Instructions will have a small special
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each processor every clock cycle. Instructions will have a small special
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buffer so that small loops can be made without any memory access penalty.
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buffer so that small loops can be made without any memory access penalty.
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(That is loops not implemented with Internal VLIW Branching.)
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(That is loops not implemented with Internal VLIW Branching.)
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I/O Interfacing:
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I/O Interfacing:
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There are memory based I/O chips connected to the memory routing network.
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There are memory based I/O chips connected to the memory routing network.
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They are able to throw interupts by signalling processors through the MP
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They are able to throw interupts by signalling processors through the MP
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Bus that their is a service request needed to be serviced.
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Bus that their is a service request needed to be serviced.
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CPU Bus Interface:
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CPU Bus Interface:
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Consist of MP Bus interface which connects to microkernel risc processor
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Consist of MP Bus interface which connects to microkernel risc processor
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and the memory i/o interface that is 128 bits in length and transfers
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and the memory i/o interface that is 128 bits in length and transfers
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data through.
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data through.
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#######################################################################
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#######################################################################
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#######################################################################
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#######################################################################
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MicroKernel Support Processor's ISA(Small risc core) -- Incomplete
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MicroKernel Support Processor's ISA(Small risc core) -- Incomplete
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This microprocessor runs part of the os and manages the mp bus.
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This microprocessor runs part of the os and manages the mp bus.
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Arithmetic:
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Arithmetic:
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ADD
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ADD
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SUB
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SUB
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SHR
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SHR
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SHL
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SHL
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ROR
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ROR
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ROL
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ROL
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RND // Random Number Generator
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RND // Random Number Generator
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Arguments: reg,reg,reg
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Arguments: reg,reg,reg
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Arguments: reg,reg,imm16
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Arguments: reg,reg,imm16
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Logic:
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Logic:
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OR
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OR
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AND
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AND
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XOR
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XOR
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NOT
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NOT
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Arguments: reg,reg,reg
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Arguments: reg,reg,reg
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Memory:
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Memory:
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LB/LW/LD(S)
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LB/LW/LD(S)
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SB/SW/SD
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SB/SW/SD
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Arguments: reg,[reg+imm16]
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Arguments: reg,[reg+imm16]
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Branch:
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Branch:
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BEQ(L)
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BEQ(L)
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BNE(L)
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BNE(L)
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BZ(L)
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BZ(L)
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BNZ(L)
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BNZ(L)
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BC(L)
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BC(L)
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BNC(L)
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BNC(L)
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J(L)
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J(L)
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JR(L)
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JR(L)
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Interupts/Special:
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Interupts/Special:
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NOP // No Operation
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NOP // No Operation
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MP(MultiProcessing) Interconnect:
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MP(MultiProcessing) Interconnect:
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MPIREAD // Write Buffer
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MPIREAD // Write Buffer
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MPIWRITE // Read Buffer
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MPIWRITE // Read Buffer
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MPIREQ? // Branch on Request Pending
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MPIREQ? // Branch on Request Pending
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Threads:
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Threads:
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TSREQ? // Branch on Thread Service Request
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TSREQ? // Branch on Thread Service Request
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Local Processor Manipulation:
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Local Processor Manipulation:
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PSTOP // Processor
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PSTOP // Processor
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PSTART
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PSTART
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TSTOP reg(threadid) // Thread
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TSTOP reg(threadid) // Thread
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