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HPC-16: Architectural Issues
M. Umair Siddiqui
Change Log
DateDescriptionAuthorsSep 03, 2005First ReleaseM. Umair Siddiqui Table of Contents
TOC \o "1-3" \h \z \u HYPERLINK \l "_Toc113479284" HPC-16: Architectural Issues PAGEREF _Toc113479284 \h i
HYPERLINK \l "_Toc113479285" Change Log PAGEREF _Toc113479285 \h ii
HYPERLINK \l "_Toc113479286" Table of Contents PAGEREF _Toc113479286 \h iii
HYPERLINK \l "_Toc113479287" 1 Introduction PAGEREF _Toc113479287 \h 1
HYPERLINK \l "_Toc113479288" 2 Basic Execution Environment PAGEREF _Toc113479288 \h 1
HYPERLINK \l "_Toc113479289" 2.1 Memory Organization PAGEREF _Toc113479289 \h 1
HYPERLINK \l "_Toc113479290" 2.2 Program Execution Registers PAGEREF _Toc113479290 \h 1
HYPERLINK \l "_Toc113479291" 2.2.1 General Purpose Registers PAGEREF _Toc113479291 \h 1
HYPERLINK \l "_Toc113479292" 2.2.2 FLAGS Register PAGEREF _Toc113479292 \h 2
HYPERLINK \l "_Toc113479293" 2.2.3 Program Counter PAGEREF _Toc113479293 \h 3
HYPERLINK \l "_Toc113479294" 2.2.4 Stack Pointer PAGEREF _Toc113479294 \h 3
HYPERLINK \l "_Toc113479295" 3 Operand Addressing PAGEREF _Toc113479295 \h 3
HYPERLINK \l "_Toc113479296" 3.1 Immediate Operands PAGEREF _Toc113479296 \h 3
HYPERLINK \l "_Toc113479297" 3.2 Register Operands PAGEREF _Toc113479297 \h 3
HYPERLINK \l "_Toc113479298" 3.3 Memory Operands PAGEREF _Toc113479298 \h 4
HYPERLINK \l "_Toc113479299" 4 Data Types PAGEREF _Toc113479299 \h 4
HYPERLINK \l "_Toc113479300" 4.1 Numeric Data types PAGEREF _Toc113479300 \h 4
HYPERLINK \l "_Toc113479301" 4.2 Pointer Data Types PAGEREF _Toc113479301 \h 4
HYPERLINK \l "_Toc113479302" 5 Alignment of Words PAGEREF _Toc113479302 \h 4
HYPERLINK \l "_Toc113479303" 6 Procedure Calls PAGEREF _Toc113479303 \h 5
HYPERLINK \l "_Toc113479304" 6.1 Stack PAGEREF _Toc113479304 \h 5
HYPERLINK \l "_Toc113479305" 6.2 Call and Ret instructions PAGEREF _Toc113479305 \h 6
HYPERLINK \l "_Toc113479306" 6.3 Procedure Linking Information PAGEREF _Toc113479306 \h 6
HYPERLINK \l "_Toc113479307" 7 Interrupts and Exceptions PAGEREF _Toc113479307 \h 7
HYPERLINK \l "_Toc113479308" 7.1 Invalid Instruction PAGEREF _Toc113479308 \h 9
HYPERLINK \l "_Toc113479309" 7.2 Alignment Exception PAGEREF _Toc113479309 \h 9
HYPERLINK \l "_Toc113479310" 7.3 Stack Error Exception PAGEREF _Toc113479310 \h 9
HYPERLINK \l "_Toc113479311" 7.4 Double Fault PAGEREF _Toc113479311 \h 9
HYPERLINK \l "_Toc113479312" 7.5 Hardware interrupt PAGEREF _Toc113479312 \h 10
HYPERLINK \l "_Toc113479313" 7.6 Software Interrupt PAGEREF _Toc113479313 \h 10
HYPERLINK \l "_Toc113479314" 8 HPC-16 Instructions PAGEREF _Toc113479314 \h 10
HYPERLINK \l "_Toc113479315" 8.1 Data Transfer Instructions PAGEREF _Toc113479315 \h 10
HYPERLINK \l "_Toc113479316" 8.2 Binary Arithmetic Instructions PAGEREF _Toc113479316 \h 11
HYPERLINK \l "_Toc113479317" 8.3 Logical Instructions PAGEREF _Toc113479317 \h 12
HYPERLINK \l "_Toc113479318" 8.4 Shift and Rotate Instructions PAGEREF _Toc113479318 \h 12
HYPERLINK \l "_Toc113479319" 8.5 Control Transfer Instructions PAGEREF _Toc113479319 \h 13
HYPERLINK \l "_Toc113479320" 8.6 Flag Control Instructions PAGEREF _Toc113479320 \h 15
HYPERLINK \l "_Toc113479321" 8.7 Miscellaneous Instructions PAGEREF _Toc113479321 \h 16
1 Introduction
In this document, architectural issues related to HPC-16 series are discussed. The architectural issues are mainly concerned with structure and behavior of the processor as seen by the programmer. It includes execution environment, addressing modes, instruction set and other programming conventions. The architectural issues usually remain constant through out all implementations.
2 Basic Execution Environment
Any program running on an HPC-16 processor is given a set of resources for executing instructions and for storing code, data, and state information. These resources make up the basic execution environment. This basic execution environment is used jointly by the application programs and the operating-system or executive running on the processor.
Address Space: Any task or program running on HPC-16 processor can address a linear address space of up to 64 Kbytes.
Basic program execution registers: The 16 general-purpose registers, the FLAGS register, SP, and the PC register comprise a basic execution environment in which to execute Hpc-16 ISA instructions.
Stack: To support procedure or subroutine calls and the passing of parameters between procedures or subroutines, a stack and stack management resources are included in the execution environment. The stack is located in memory.
Figure: 2.1 - Basic execution environment
2.1 Memory Organization
Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical address space ranges from zero to a maximum of 216 - 1.
2.2 Program Execution Registers
The processor provides 16 basic program execution registers for use in general system and application programming. Shown in Figure 4-1, these registers can be grouped as follows:
2.2.1 General Purpose Registers
There are sixteen 16-bit general purpose registers R0 - R15 present in processor. These registers R0 - R15 are provided for holding the following items:
Operands for logical and arithmetic operations
Operands for address calculations
Memory pointers
2.2.2 FLAGS Register
The 5-bit FLAGS register contains a group of status flags, and a flag. Following initialization of the processor (by asserting the RESET pin), the state of the FLAGS register is 000002. Some of the flags in the FLAGS register can be modified directly, using special-purpose instructions. There are no instructions that allow the whole register to be examined or modified directly. The PUSHF and POPF instructions can be used to move groups of flags to and from the procedure stack. After the contents of the FLAGS register have been transferred to the procedure stack, the flags can be examined and modified.
The bits (4 1) are status flags, indicate the results of arithmetic instructions, such as the ADD, SUB, ADC and SBB instructions. The status flag functions are:
ZF (bit 1) Zero flag: Set if the result is zero; cleared otherwise.
SF (bit 2) Sign flag: Set equal to the most-significant bit of the result, which is the sign bit of a signed integer. (0 indicates a positive value and 1 indicates a negative value.)
OF (bit 3) Overflow flag: Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise. This flag indicates an overflow condition for signed-integer (twos complement) arithmetic.
CF (bit 4) Carry flag: Set if an arithmetic operation generates a carry or a borrow out of the most-significant bit of the result; cleared otherwise. This flag indicates an overflow condition for unsigned-integer arithmetic. It is also used in multiple-precision arithmetic.
Of these status flags, only the CF flag can be modified directly, using the STC, CLC, and CMC instructions. The status flags allow a single arithmetic operation to produce results for two different data types: unsigned integers and signed integers. If the result of an arithmetic operation is treated as an unsigned integer, the CF flag indicates an out-of-range condition (carry or borrow); if treated as a signed integer (twos complement number), the OF flag indicates a carry or borrow. The SF flag indicates the sign of a signed integer. The ZF flag indicates either a signed- or an unsigned integer zero. When performing multiple-precision arithmetic on integers, the CF flag is used in conjunction with add with carry (ADC) and subtract with borrow (SBB) instructions to propagate a carry or borrow from one computation to the next. The condition instructions Jcc (jump on condition code cc) and INTO (interrupt on overflow) use one or more of the status flags as condition codes and test them for branch.
There is only one system flag: IF (bit 0) Interrupt enable flag. It controls the response of the processor to external interrupt requests which are maskable though software. Set to respond to maskable interrupts; cleared to inhibit maskable interrupts.
When a interrupt or exception is raised, the processor automatically saves the state of the FLAGS register on the procedure stack.
2.2.3 Program Counter
The program counter (PC) register contains the address in memory for the next instruction to be executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or backwards by a number of instructions when executing JMP, Jcc, CALL, RET, and IRET instructions.
The PC register cannot be accessed directly by software; it is controlled implicitly by control transfer instructions (such as JMP, Jcc, CALL, and RET), interrupts, and exceptions. The only way to read the PC register is to execute a CALL instruction and then read the value of the return instruction pointer from the procedure stack. The PC register can be loaded indirectly by modifying the value of a return instruction pointer on the procedure stack and executing a return instruction (RET or IRET).
2.2.4 Stack Pointer
The stack pointer (SP) register contain the address of top of stack. The processor use stack for pushing PC during execution of CALL instruction, it also uses stack for processing interrupts (both hardware and software) and exception.
3 Operand Addressing
HPC-16 machine-instructions act on zero or more operands. Some operands are specified explicitly and others are implicit. The data for a source operand can be located in: (1) The instruction itself (an immediate operand), (2) A register and (3) A memory location. When an instruction returns data to a destination operand, it can be returned to: (1) A register and (2) A memory location.
3.1 Immediate Operands
Some instructions use data encoded in the instruction itself as a source operand. These operands are called immediate operands. All arithmetic instructions allow the source operand to be an immediate value. The maximum value allowed for an immediate operand is the maximum value of an unsigned 16-bit word integer.
3.2 Register Operands
Register operands (as source or destination) can be any of the following registers, depending on the instruction being executed:
16-bit general-purpose registers (R0 - R15)
Stack pointer (SP)
FLAGS register
3.3 Memory Operands
Source and destination operands in memory are referenced by means of a physical address. The memory address can be specified using base (value in general purpose register or SP) and base/index + 16-bit signed displacement. The resulting address is called an effective address. Since HPC-16 is load-store RISC, it only uses memory operands either for loading data into register or storing the data in register to memory.
A base alone represents an indirect address of the operand. Since the value in the base register can change, it can be used for dynamic storage of variables and data structures.
A base/index register and a displacement can be used to access a field of a record/array; the base register holds the address of the beginning of the record/array, while the displacement is static offset to the field. Another way to use this addressing mode is that: displacement locates the beginning of the array, and index register holds the subscript of desired array element.
4 Data Types
The fundamental data types of the HPC-16 architecture are bytes, words. A byte is eight bits; a word is 2 bytes (16 bits). A subset of the HPC-16 architecture instructions operates on these fundamental data types without any additional operand typing. The HPC-16 is big-endian machine, the high byte (bits 15 through 8) of word occupies the low address in memory and that address is also the address of the operand.
4.1 Numeric Data types
The HPC-16 architecture defines two types of integers: unsigned and signed. Unsigned integers are ordinary binary values ranging from 0 to the maximum positive number that can be encoded in the selected operand size. Signed integers are twos complement binary values that can be used to represent both positive and negative integer values. Some integer instructions (such as the ADD, SUB instructions) operate on either unsigned or signed integer operands.
4.2 Pointer Data Types
Pointers are addresses of locations in memory. Since the addressable memory is 64K, therefore pointers are of 16-bit size.
5 Alignment of Words
16-bit words need to be aligned in memory on even boundaries (addresses divisible by two). Access to unaligned words result in alignment exception. However there is no alignment restriction on 8-bit bytes.
Figure: 5.1 Byte and Word Alignment
6 Procedure Calls
The processor supports procedure calls using "CALL" and "RET" instructions. This procedure call mechanism use the procedure stack, commonly referred to simply as "the stack", to save the state of the calling procedure, and store local variables for the currently executing procedure.
6.1 Stack
The stack is a contiguous array of memory locations. The stack can be located any where in the linear address space for the program and can be up to 64Kbytes long (complete address space).
Figure: 6.1 Stack
Items are placed on the stack using the push instruction and removed from the stack using the POP instruction. When an item is placed onto stack, the processor decrements the SP (or sp, we will use both interchangeably) register, then writes the item at the new top of stack. When an item is popped off the stack, the processor reads the item from the top of the stack, and then increments the SP register. In this manner, the stack grows down in memory (towards lesser addresses) when items are pushed on the stack and shrinks up (towards greater addresses) when the items are popped from the stack.
To set the stack, the program or operating system/executive must do the following:
Reserve the area for stack
Load the stack pointer for the stack into the SP register using a MOV or LI instruction.
The stack pointer for a stack segment should be aligned on 16-bit (word). The processor checks the stack pointer alignment. Misaligning the stack pointer will result in stack error exception.
6.2 Call and Ret instructions
When executing a call, the processor does the following:
Pushes the current value of the PC register on the stack.
Loads the address of the called procedure in the PC register.
Begins execution of the called procedure.
When executing a return, the processor performs these actions:
Pops the top-of-stack value (the return instruction pointer) into the PC register.
Resumes execution of the calling procedure.
6.3 Procedure Linking Information
The processor provides two pointers for linking of procedures: the stack-frame base pointer and the return instruction pointer. These pointers permit reliable and coherent linking of procedures.
Stack-frame base pointer: The stack is typically divided into frames. Each stack frame can then contain local variables, parameters to be passed to another procedure, and procedure linking information. The stack-frame base pointer (contained in bp/fp register, the software can use general purpose register R15 as bp/fp) identifies a fixed reference point within the stack frame for the called procedure. To use the stack-frame base pointer, the called procedure typically copies the contents of the SP register into the bp/fp register prior to pushing any local variables on the stack. The stack-frame base pointer then permits easy access to data structures passed on the stack, to the return instruction pointer, and to local variables added to the stack by the called procedure.
Return instruction pointer: Prior to branching to the first instruction of the called procedure, the CALL instruction pushes the address in the PC register onto the current stack. This address is then called the return-instruction pointer and it points to the instruction where execution of the calling procedure should resume following a return from the called procedure. Upon returning from a called procedure, the RET instruction pops the return-instruction pointer from the stack back into the PC register. Execution of the calling procedure then resumes.
The processor does not keep track of the location of the return-instruction pointer. It is thus up to the programmer to insure that stack pointer is pointing to the return-instruction pointer on the stack, prior to issuing a RET instruction. A common way to reset the stack pointer to the point to the return-instruction pointer is to move the contents of the BP register into the sp register. If the bp/fp register is loaded with the stack pointer immediately following a procedure call, it should point to the return-instruction pointer on the stack.
The processor does not require that the return instruction pointer point back to the calling procedure. Prior to executing the RET instruction; the return-instruction pointer can be manipulated in software to point to any address in the memory. Performing such an operation, however, should be undertaken very cautiously, using only well defined code entry points.
7 Interrupts and Exceptions
The processor provides two mechanisms for interrupting program execution, interrupts and exceptions:
An interrupt is an asynchronous event that is typically triggered by an I/O device.
An exception is a synchronous event that is generated when the processor detects one or more predefined conditions while executing an instruction.
The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception is signaled, the processor halts execution of the current program and switches to a handler procedure that has been written specifically to handle the interrupt or exception condition. The processor responds to an interrupt or exception with an implicit call to an interrupt or exception handler. The processor uses the interrupt or exception vector number as an index into an interrupt vector table. There are total 16 interrupt which separated by 8-bytes, the application can write exception/interrupt handler procedures in these locations or may jump to handler located at other memory locations.
The HPC-16 Architecture defines 5 predefined interrupts and exceptions and 11 user defined interrupts, which are associated with entries in the IVT. Each interrupt and exception in the IVT is identified with a number, called a vector. Table 4.1 lists the interrupts and exceptions with entries in the IVT and their respective vector numbers. Vectors 0 through 4 are the predefined exceptions, and vectors 5 through 15 are the user-defined interrupts, called maskable interrupts.
When the processor detects an interrupt or exception, it executes an implicit call to a handler procedure. The processor performs following actions when calling an interrupt or exception handler:
Pushes the current contents of the FLAGS, and PC registers respectively on the stack.
Loads the new program counter value with 8 * vector no.
Clears the IF flag in the FLAGS register
Begins execution of the handler procedure
A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar to the far RET instruction, except that it also restores the contents of the FLAGS register for the interrupted procedure.
Restores the PC registers to their values prior to the interrupt or exception.
Restores the FLAGS register
Increments the stack pointer appropriately
Resumes execution of the interrupted procedure
Table: 7.1 Interrupt Vector Locations
Vector No.DescriptionSourceMemory Location,0OverflowINTO instruction0000h1Invalid instructionReserved Opcode0008h2Alignment errorAny memory reference0010h3Stack ErrorStack misalignment0018h4Double faultStack misalignment while executing maskable interrupt or during invalid instruction, alignment error 0020h5 15Maskable InterruptsExternal interrupt from INTR pin or INT n instruction0028h - 0078h
7.1 Invalid Instruction
This exception is raise when instruction contains invaild/reserved opcode, subop fields.
7.2 Alignment Exception
All the 16-bit word data or instruction, should be aligned on even address (i.e contain zero in least significant bit). Accessing misaligned word will cause this interrupt. However this instruction will not be raised, in case of lbzx/lbsx/sb instruction.
7.3 Stack Error Exception
If the stack contains odd address, for this exception CPU behavior is changed, CPU internally save offending SP content, then SP is asynchronously set to predefined value (0x0000). CPU pushes old SP value, FLAGS and PC and jump to Stack Exception vector location.
Figure: 7.1 Stack Error Exception
7.4 Double Fault
It may also possible, that some interrupt or exception (other than stack error) occur. Now processor needs to push flags and PC but if at this point, SP contain invalid value then this exception will occur. In this exception like Stack error, CPU internally saves the invalid contents of SP then SP is asynchronously preset to predefined value (0x0000). CPU pushes old interrupt no, old SP value, FLAGS and PC, then jump to Double Fault Exception vector location.
Figure: 7.2 Double Fault
7.5 Hardware interrupt
The hardware interrupt is raised by asserting INTR_I pin of CPU. The INTR_I generating source is required to assert it continuously until it is not recognized. The CPU first inspect the IF status (i.e can be masked by software by clearing IF) before checking INTR_I. Before pushing the FLAGS and PC, it generates a special read cycle to get the vector no. from slave device. In this read cycle IACK_CYC_O pin is asserted by CPU to indicate that it is special read cycle. The slave is suppose to put 4-bit interrupt number on databus(11..8), and deassert the INTR_I pin.
7.6 Software Interrupt
The software interrupt is generated by INT n and INTO instructions. The IF is not checked. The INT n and INTO allow a program or task to explicitly call an interrupt or exception handler. The INT n instruction uses an interrupt vector as an argument, which allows a program to call any interrupt handler.
The INTO instruction explicitly calls the overflow exception handler if the overflow flag (OF) in the FLAGS register is set. The OF flag indicates overflow on arithmetic instructions, but it does not automatically raise an overflow exception. An overflow exception can only be raised explicitly in either of the following ways:
Execute the INTO instruction.
Test the OF flag and execute the INT n instruction with an argument of 0 (the vector number of the overflow exception) if the flag is set.
8 HPC-16 Instructions
HPC-16 instruction set include several instructions, which shown in Appendix A. These instructions can divided into seven major categories, which are given below:
8.1 Data Transfer Instructions
The data transfer instructions move bytes, words both between memory and the processors registers and between registers. For the purpose of this discussion, these instructions are divided into subordinate subgroups that provide for:
General data movement
Stack manipulation
General Data Movement Instructions: The MOV (move) instruction transfer data between general-purpose registers (GPRs) and SP. The LI (load immediate) load constant 16-bit data into GPR and SP. The LD instruction load data from memory to GPR and ST instruction store data from GPR into memory. Separate mnemonics are provided for byte loading and storing, all the byte operands loaded from memory: LBSX sign extends the byte operand and load the result into GPR while LBZX zero extends the byte operand and then load result into GPR. SB stores the lower byte of GPR into memory.
Stack manipulation Instructions: The PUSH instruction decrements the stack pointer (contained in the SP register), then copies the source operand to the top of stack. It operates on GPR operands only. The POP instruction copies the word at the current top of stack (indicated by the SP register) to the location specified with the destination operand. It then increments the SP register to point to the new top of stack. The destination operand specifies a GPR only.
8.2 Binary Arithmetic Instructions
Binary arithmetic instructions operate on 16-bit numeric data encoded as signed or unsigned binary integers. For the purpose of this discussion, these instructions are divided subordinate subgroups of instructions that:
Add and subtract
Increment and decrement
Compare
Add and Subtract: The ADD (add integers), ADC (add integers with carry), SUB (subtract integers), and SBB (subtract integers with borrow) instructions perform addition and subtraction operations on signed or unsigned integer operands. The operands can be two GPRs, GPR-immediate or SP-immediate. The ADD instruction computes the sum of two integer operands. The ADC instruction computes the sum of two integer operands, plus 1 if the CF flag is set. This instruction is used to propagate a carry when adding numbers in stages. The SUB instruction computes the difference of two integer operands. The SBB instruction computes the difference of two integer operands, minus 1 if the CF flag is set. This instruction is used to propagate a borrow when subtracting numbers in stages. SP related instructions support only SUB and ADD operation.
Increment and Decrement Instructions: The INC (increment) and DEC (decrement) instructions add 1 to or subtract 1 from an unsigned integer operand (GPR) respectively, without affecting CF flag. A primary use of these instructions is for implementing counters.
Arithmetic Comparison: The CMP (compare) instruction computes the difference between two integer operands (two GPRs or GPR-immediate) and updates the OF, SF, ZF, AF, PF, and CF flags according to the result. The source operands are not modified, nor is the result saved. The CMP instruction is commonly used in conjunction with a Jcc (conditional jump) instruction.
8.3 Logical Instructions
The logical instructions AND, OR, XOR (exclusive or), and NOT perform the standard Boolean operations for which they are named. The AND, OR, and XOR instructions require two operands (two GPRs or GPR-immediate); the NOT instruction operates on a single operand (GPR). The TEST instruction performs a logical AND of two operands and sets the SF and ZF flags according to the results. The flags can then be tested by the conditional jump instructions. The TEST instruction differs from the AND instruction in that it does not alter either of the operands.
8.4 Shift and Rotate Instructions
The shift and rotate instructions rearrange the bits within an operand. For the purpose of this discussion, these instructions are further divided subordinate subgroups of instructions that:
Shift bits
Rotate bits
Shift Instructions: The SAL (shift arithmetic left), SHL (shift logical left), SAR (shift arithmetic right), SHR (shift logical right) instructions perform an arithmetic or logical shift of the bits in a word. The SAL and SHL instructions perform the same operation. They shift the source operand left by from 1 to 15 bit positions. Empty bit positions are cleared. The CF flag is loaded with the last bit shifted out of the operand. The SHR instruction shifts the source operand right by from 1 to 15 bit positions. As with the SHL/SAL instruction, the empty bit positions are cleared and the CF flag is loaded with the last bit shifted out of the operand. The SAR instruction shifts the source operand right by from 1 to 15 bit positions. This instruction differs from the SHR instruction in that it preserves the sign of the source operand by clearing empty bit positions if the operand is positive or setting the empty bits if the operand is negative. Again, the CF flag is loaded with the last bit shifted out of the operand.
Rotate Instructions: The ROL (rotate left), ROR (rotate right), RCL (rotate through carry left) and RCR (rotate through carry right) instructions rotate the bits in the destination operand out of one end and back through the other end. Unlike a shift, no bits are lost during a rotation. The rotate count can range from 0 to 15. The ROL instruction rotates the bits in the operand to the left (toward more significant bit locations). The ROR instruction rotates the operand right (toward less significant bit locations). The RCL instruction rotates the bits in the operand to the left, through the CF flag. This instruction treats the CF flag as a one-bit extension on the upper end of the operand. Each bit that exits from the most significant bit location of the operand moves into the CF flag. At the same time, the bit in the CF flag enters the least significant bit location of the operand. The RCR instruction rotates the bits in the operand to the right through the CF flag. For all the rotate instructions, the CF flag always contains the value of the last bit rotated out of the operand, even if the instruction does not use the CF flag as an extension of the operand. The value of this flag can then be tested by a conditional jump instruction (JC or JNC).
8.5 Control Transfer Instructions
The processor provides both conditional and unconditional control transfer instructions to direct the flow of program execution. Conditional transfers are taken only for specified states of the status flags in the FLAGS register. Unconditional control transfers are always executed. For the purpose of this discussion, these instructions are further divided subordinate subgroups that process:
Unconditional transfers
Conditional transfers
Software interrupts
Unconditional Transfer Instructions: The JMP, CALL and RET instructions transfer program control to another location (destination address) in the instruction stream. The destination can be any where within 64K addressable memory.
Jump instruction - The JMP (jump) instruction unconditionally transfers program control to a destination instruction. The transfer is one-way; that is, a return address is not saved. A destination operand specifies the address (the instruction pointer) of the destination instruction. The address can be a relative address or an absolute address.
A relative address is a displacement (offset) with respect to the address in the PC register. The destination address is formed by adding the displacement to the address in the PC register. The displacement is specified with a signed integer, present either as part of instruction (11 bit sign extended immediate constant) or present in GPR, allowing jumps either forward or backward in the instruction stream. An absolute address is the physical address of memory. Here, target address is value inside GPR. This value is directly copied into PC register.
Call and return instructions - The CALL (call procedure) and RET (return from procedure) instructions allow a jump from one procedure (or subroutine) to another and a subsequent jump back (return) to the calling procedure. The CALL instruction transfers program control from the current (or calling procedure) to another procedure (the called procedure). To allow a subsequent return to the calling procedure, the CALL instruction saves the current contents of the PC register on the stack before jumping to the called procedure. The PC register (prior to transferring program control) contains the address of the instruction following the CALL instruction. When this address is pushed on the stack, it is referred to as the return instruction pointer or return address. The address of the called procedure (the address of the first instruction in the procedure being jumped to) is specified in a CALL instruction the same way as it is in a JMP instruction. The address can be specified as a relative address or an absolute address.
The RET instruction transfers program control from the procedure currently being executed (the called procedure) back to the procedure that called it (the calling procedure). Transfer of control is accomplished by copying the return instruction pointer from the stack into the PC register. Program execution then continues with the instruction pointed to by the PC register.
Conditional transfer instructions: The conditional transfer instructions execute jumps that transfer program control to another instruction in the instruction stream if specified conditions are met. The conditions for control transfer are specified with a set of condition codes that define various states of the status flags (CF, ZF, OF and SF) in the FLAGS register. The Jcc (conditional) jump instructions transfer program control to a destination instruction if the conditions specified with the condition code (cc) associated with the instruction are satisfied. If the condition is not satisfied, execution continues with the instruction following the Jcc instruction. As with the JMP instruction, the transfer is one-way; that is, a return address is not saved.
Table: 8.1 Conditional Jump Instructions
Instruction MnemonicsCondition (Flags states)DescriptionUnsigned Conditional JumpsJA/JNBE(CF or ZF) = 0Above/ not below or equalJAE/JNBCF = 0Above or equal/ not belowJB/ JNAECF = 1Below/ not above or equalJBE/ JNA (CF or ZF) = 1Below or equal/ not aboveJCCF = 1CarryJE/JZZF = 1Equal / zeroJNCCF = 0Not carryJNE/ JNZZF = 0Not equal /not zeroSigned Conditional JumpsJG/ JNLE((SF xor OF) or ZF) = 0Greater/ not less or equal JGE/ JNL(SF xor OF) = 0Greater or equal/ not lessJL/JNGE(SF xor OF) = 1Less/ not greater or equal JLE/ JNG((SF xor OF) or ZF) = 1Less or equal / not greaterJNOOF = 0Not OverflowJNSSF = 0Not sign (non-negative)JOOF = 1OverflowJSSF = 1Sign (negative)
The target address is specified in a Jcc instruction as a relative address (7-bit sign extended immediate constant). Table shows the mnemonics for the Jcc instructions and the conditions being tested for each instruction. The condition code mnemonics are appended to the letter "J" to form the mnemonic for a Jcc instruction. The instructions are divided into two groups: unsigned and signed conditional jumps. These groups correspond to the results of operations performed on unsigned and signed integers respectively. Those instructions listed as pairs (for example, JA/JNBE) are alternate names for the same instruction.
Software Interrupt Instructions: The INT n (software interrupt) and INTO (interrupt on overflow) instructions allow a program to explicitly raise a specified interrupt or exception, which in turn causes the handler routine for the interrupt or exception to be called. The INT n instruction can raise any of the processors interrupts or exceptions by encoding the vector number or the interrupt or exception in the instruction. The contents of the FLAGS register are automatically stored on the stack along with the return instruction pointer when the processor services an interrupt. The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted procedure. The IRET instruction performs a similar operation to the RET instruction, except that it also restores the FLAGS register from the stack. The INTO instruction raises the overflow exception if the OF flag is set. If the flag is clear, execution continues without raising the exception. This instruction allows software to access the overflow exception handler explicitly to check for overflow conditions.
8.6 Flag Control Instructions
The Flag Control instructions allow the state of selected flags in the FLAGS register to be read or modified. For the purpose of this discussion, these instructions are further divided subordinate subgroups of instructions that manipulate:
Carry flag
The FLAGS register
Interrupt flag
Carry Flag Instructions: The STC (set carry flag), CLC (clear carry flag), and CMC (complement carry flag) instructions allow the CF flags in the FLAGS register to be modified directly. They are typically used to initialize the CF flag to a known state before an instruction that uses the flag in an operation is executed. They are also used in conjunction with the rotate-with-carry instructions (RCL and RCR).
FLAGS Transfer Instructions: The PUSHF (push flags) and POPF (pop flags) instructions copy the flags in the FLAGS register to and from the stack. The PUSHF pushes the FLAGS register onto the stack. The POPF instruction pops a word from the stack into the FLAGS register.
Interrupt Flag Instructions: The STI (set interrupt flag) and CTI (clear interrupt flag) instructions allow the interrupt IF flag in the FLAGS register to be modified directly.
8.7 Miscellaneous Instructions
The NOP instruction increments the PC register to point at the next instruction, but affect nothing else. HLT instruction stops further instruction execution, set the interrupt flag and places the processor in a HALTED state. An enabled interrupt or the RESET signal will resume execution. If an interrupt is used to resume execution after a HLT instruction, the saved instruction pointer (PC) points to the instruction following the HLT instruction.
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HPC-16: Architectural Issues
M. Umair Siddiqui
Change Log
DateDescriptionAuthorsSep 03, 2005First ReleaseM. Umair Siddiqui Table of Contents
TOC \o "1-3" \h \z \u HYPERLINK \l "_Toc113479284" HPC-16: Architectural Issues PAGEREF _Toc113479284 \h i
HYPERLINK \l "_Toc113479285" Change Log PAGEREF _Toc113479285 \h ii
HYPERLINK \l "_Toc113479286" Table of Contents PAGEREF _Toc113479286 \h iii
HYPERLINK \l "_Toc113479287" 1 Introduction PAGEREF _Toc113479287 \h 1
HYPERLINK \l "_Toc113479288" 2 Basic Execution Environment PAGEREF _Toc113479288 \h 1
HYPERLINK \l "_Toc113479289" 2.1 Memory Organization PAGEREF _Toc113479289 \h 1
HYPERLINK \l "_Toc113479290" 2.2 Program Execution Registers PAGEREF _Toc113479290 \h 1
HYPERLINK \l "_Toc113479291" 2.2.1 General Purpose Registers PAGEREF _Toc113479291 \h 1
HYPERLINK \l "_Toc113479292" 2.2.2 FLAGS Register PAGEREF _Toc113479292 \h 2
HYPERLINK \l "_Toc113479293" 2.2.3 Program Counter PAGEREF _Toc113479293 \h 3
HYPERLINK \l "_Toc113479294" 2.2.4 Stack Pointer PAGEREF _Toc113479294 \h 3
HYPERLINK \l "_Toc113479295" 3 Operand Addressing PAGEREF _Toc113479295 \h 3
HYPERLINK \l "_Toc113479296" 3.1 Immediate Operands PAGEREF _Toc113479296 \h 3
HYPERLINK \l "_Toc113479297" 3.2 Register Operands PAGEREF _Toc113479297 \h 3
HYPERLINK \l "_Toc113479298" 3.3 Memory Operands PAGEREF _Toc113479298 \h 4
HYPERLINK \l "_Toc113479299" 4 Data Types PAGEREF _Toc113479299 \h 4
HYPERLINK \l "_Toc113479300" 4.1 Numeric Data types PAGEREF _Toc113479300 \h 4
HYPERLINK \l "_Toc113479301" 4.2 Pointer Data Types PAGEREF _Toc113479301 \h 4
HYPERLINK \l "_Toc113479302" 5 Alignment of Words PAGEREF _Toc113479302 \h 4
HYPERLINK \l "_Toc113479303" 6 Procedure Calls PAGEREF _Toc113479303 \h 5
HYPERLINK \l "_Toc113479304" 6.1 Stack PAGEREF _Toc113479304 \h 5
HYPERLINK \l "_Toc113479305" 6.2 Call and Ret instructions PAGEREF _Toc113479305 \h 6
HYPERLINK \l "_Toc113479306" 6.3 Procedure Linking Information PAGEREF _Toc113479306 \h 6
HYPERLINK \l "_Toc113479307" 7 Interrupts and Exceptions PAGEREF _Toc113479307 \h 7
HYPERLINK \l "_Toc113479308" 7.1 Invalid Instruction PAGEREF _Toc113479308 \h 9
HYPERLINK \l "_Toc113479309" 7.2 Alignment Exception PAGEREF _Toc113479309 \h 9
HYPERLINK \l "_Toc113479310" 7.3 Stack Error Exception PAGEREF _Toc113479310 \h 9
HYPERLINK \l "_Toc113479311" 7.4 Double Fault PAGEREF _Toc113479311 \h 9
HYPERLINK \l "_Toc113479312" 7.5 Hardware interrupt PAGEREF _Toc113479312 \h 10
HYPERLINK \l "_Toc113479313" 7.6 Software Interrupt PAGEREF _Toc113479313 \h 10
HYPERLINK \l "_Toc113479314" 8 HPC-16 Instructions PAGEREF _Toc113479314 \h 10
HYPERLINK \l "_Toc113479315" 8.1 Data Transfer Instructions PAGEREF _Toc113479315 \h 10
HYPERLINK \l "_Toc113479316" 8.2 Binary Arithmetic Instructions PAGEREF _Toc113479316 \h 11
HYPERLINK \l "_Toc113479317" 8.3 Logical Instructions PAGEREF _Toc113479317 \h 12
HYPERLINK \l "_Toc113479318" 8.4 Shift and Rotate Instructions PAGEREF _Toc113479318 \h 12
HYPERLINK \l "_Toc113479319" 8.5 Control Transfer Instructions PAGEREF _Toc113479319 \h 13
HYPERLINK \l "_Toc113479320" 8.6 Flag Control Instructions PAGEREF _Toc113479320 \h 15
HYPERLINK \l "_Toc113479321" 8.7 Miscellaneous Instructions PAGEREF _Toc113479321 \h 16
1 Introduction
In this document, architectural issues related to HPC-16 series are discussed. The architectural issues are mainly concerned with structure and behavior of the processor as seen by the programmer. It includes execution environment, addressing modes, instruction set and other programming conventions. The architectural issues usually remain constant through out all implementations.
2 Basic Execution Environment
Any program running on an HPC-16 processor is given a set of resources for executing instructions and for storing code, data, and state information. These resources make up the basic execution environment. This basic execution environment is used jointly by the application programs and the operating-system or executive running on the processor.
Address Space: Any task or program running on HPC-16 processor can address a linear address space of up to 64 Kbytes.
Basic program execution registers: The 16 general-purpose registers, the FLAGS register, SP, and the PC register comprise a basic execution environment in which to execute Hpc-16 ISA instructions.
Stack: To support procedure or subroutine calls and the passing of parameters between procedures or subroutines, a stack and stack management resources are included in the execution environment. The stack is located in memory.
Figure: 2.1 - Basic execution environment
2.1 Memory Organization
Physical memory is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address, called a physical address. The physical address space ranges from zero to a maximum of 216 - 1.
2.2 Program Execution Registers
The processor provides 16 basic program execution registers for use in general system and application programming. Shown in Figure 4-1, these registers can be grouped as follows:
2.2.1 General Purpose Registers
There are sixteen 16-bit general purpose registers R0 - R15 present in processor. These registers R0 - R15 are provided for holding the following items:
Operands for logical and arithmetic operations
Operands for address calculations
Memory pointers
2.2.2 FLAGS Register
The 5-bit FLAGS register contains a group of status flags, and a flag. Following initialization of the processor (by asserting the RESET pin), the state of the FLAGS register is 000002. Some of the flags in the FLAGS register can be modified directly, using special-purpose instructions. There are no instructions that allow the whole register to be examined or modified directly. The PUSHF and POPF instructions can be used to move groups of flags to and from the procedure stack. After the contents of the FLAGS register have been transferred to the procedure stack, the flags can be examined and modified.
The bits (4 1) are status flags, indicate the results of arithmetic instructions, such as the ADD, SUB, ADC and SBB instructions. The status flag functions are:
ZF (bit 1) Zero flag: Set if the result is zero; cleared otherwise.
SF (bit 2) Sign flag: Set equal to the most-significant bit of the result, which is the sign bit of a signed integer. (0 indicates a positive value and 1 indicates a negative value.)
OF (bit 3) Overflow flag: Set if the integer result is too large a positive number or too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise. This flag indicates an overflow condition for signed-integer (twos complement) arithmetic.
CF (bit 4) Carry flag: Set if an arithmetic operation generates a carry or a borrow out of the most-significant bit of the result; cleared otherwise. This flag indicates an overflow condition for unsigned-integer arithmetic. It is also used in multiple-precision arithmetic.
Of these status flags, only the CF flag can be modified directly, using the STC, CLC, and CMC instructions. The status flags allow a single arithmetic operation to produce results for two different data types: unsigned integers and signed integers. If the result of an arithmetic operation is treated as an unsigned integer, the CF flag indicates an out-of-range condition (carry or borrow); if treated as a signed integer (twos complement number), the OF flag indicates a carry or borrow. The SF flag indicates the sign of a signed integer. The ZF flag indicates either a signed- or an unsigned integer zero. When performing multiple-precision arithmetic on integers, the CF flag is used in conjunction with add with carry (ADC) and subtract with borrow (SBB) instructions to propagate a carry or borrow from one computation to the next. The condition instructions Jcc (jump on condition code cc) and INTO (interrupt on overflow) use one or more of the status flags as condition codes and test them for branch.
There is only one system flag: IF (bit 0) Interrupt enable flag. It controls the response of the processor to external interrupt requests which are maskable though software. Set to respond to maskable interrupts; cleared to inhibit maskable interrupts.
When a interrupt or exception is raised, the processor automatically saves the state of the FLAGS register on the procedure stack.
2.2.3 Program Counter
The program counter (PC) register contains the address in memory for the next instruction to be executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or backwards by a number of instructions when executing JMP, Jcc, CALL, RET, and IRET instructions.
The PC register cannot be accessed directly by software; it is controlled implicitly by control transfer instructions (such as JMP, Jcc, CALL, and RET), interrupts, and exceptions. The only way to read the PC register is to execute a CALL instruction and then read the value of the return instruction pointer from the procedure stack. The PC register can be loaded indirectly by modifying the value of a return instruction pointer on the procedure stack and executing a return instruction (RET or IRET).
2.2.4 Stack Pointer
The stack pointer (SP) register contain the address of top of stack. The processor use stack for pushing PC during execution of CALL instruction, it also uses stack for processing interrupts (both hardware and software) and exception.
3 Operand Addressing
HPC-16 machine-instructions act on zero or more operands. Some operands are specified explicitly and others are implicit. The data for a source operand can be located in: (1) The instruction itself (an immediate operand), (2) A register and (3) A memory location. When an instruction returns data to a destination operand, it can be returned to: (1) A register and (2) A memory location.
3.1 Immediate Operands
Some instructions use data encoded in the instruction itself as a source operand. These operands are called immediate operands. All arithmetic instructions allow the source operand to be an immediate value. The maximum value allowed for an immediate operand is the maximum value of an unsigned 16-bit word integer.
3.2 Register Operands
Register operands (as source or destination) can be any of the following registers, depending on the instruction being executed:
16-bit general-purpose registers (R0 - R15)
Stack pointer (SP)
FLAGS register
3.3 Memory Operands
Source and destination operands in memory are referenced by means of a physical address. The memory address can be specified using base (value in general purpose register or SP) and base/index + 16-bit signed displacement. The resulting address is called an effective address. Since HPC-16 is load-store RISC, it only uses memory operands either for loading data into register or storing the data in register to memory.
A base alone represents an indirect address of the operand. Since the value in the base register can change, it can be used for dynamic storage of variables and data structures.
A base/index register and a displacement can be used to access a field of a record/array; the base register holds the address of the beginning of the record/array, while the displacement is static offset to the field. Another way to use this addressing mode is that: displacement locates the beginning of the array, and index register holds the subscript of desired array element.
4 Data Types
The fundamental data types of the HPC-16 architecture are bytes, words. A byte is eight bits; a word is 2 bytes (16 bits). A subset of the HPC-16 architecture instructions operates on these fundamental data types without any additional operand typing. The HPC-16 is big-endian machine, the high byte (bits 15 through 8) of word occupies the low address in memory and that address is also the address of the operand.
4.1 Numeric Data types
The HPC-16 architecture defines two types of integers: unsigned and signed. Unsigned integers are ordinary binary values ranging from 0 to the maximum positive number that can be encoded in the selected operand size. Signed integers are twos complement binary values that can be used to represent both positive and negative integer values. Some integer instructions (such as the ADD, SUB instructions) operate on either unsigned or signed integer operands.
4.2 Pointer Data Types
Pointers are addresses of locations in memory. Since the addressable memory is 64K, therefore pointers are of 16-bit size.
5 Alignment of Words
16-bit words need to be aligned in memory on even boundaries (addresses divisible by two). Access to unaligned words result in alignment exception. However there is no alignment restriction on 8-bit bytes.
Figure: 5.1 Byte and Word Alignment
6 Procedure Calls
The processor supports procedure calls using "CALL" and "RET" instructions. This procedure call mechanism use the procedure stack, commonly referred to simply as "the stack", to save the state of the calling procedure, and store local variables for the currently executing procedure.
6.1 Stack
The stack is a contiguous array of memory locations. The stack can be located any where in the linear address space for the program and can be up to 64Kbytes long (complete address space).
Figure: 6.1 Stack
Items are placed on the stack using the push instruction and removed from the stack using the POP instruction. When an item is placed onto stack, the processor decrements the SP (or sp, we will use both interchangeably) register, then writes the item at the new top of stack. When an item is popped off the stack, the processor reads the item from the top of the stack, and then increments the SP register. In this manner, the stack grows down in memory (towards lesser addresses) when items are pushed on the stack and shrinks up (towards greater addresses) when the items are popped from the stack.
To set the stack, the program or operating system/executive must do the following:
Reserve the area for stack
Load the stack pointer for the stack into the SP register using a MOV or LI instruction.
The stack pointer for a stack segment should be aligned on 16-bit (word). The processor checks the stack pointer alignment. Misaligning the stack pointer will result in stack error exception.
6.2 Call and Ret instructions
When executing a call, the processor does the following:
Pushes the current value of the PC register on the stack.
Loads the address of the called procedure in the PC register.
Begins execution of the called procedure.
When executing a return, the processor performs these actions:
Pops the top-of-stack value (the return instruction pointer) into the PC register.
Resumes execution of the calling procedure.
6.3 Procedure Linking Information
The processor provides two pointers for linking of procedures: the stack-frame base pointer and the return instruction pointer. These pointers permit reliable and coherent linking of procedures.
Stack-frame base pointer: The stack is typically divided into frames. Each stack frame can then contain local variables, parameters to be passed to another procedure, and procedure linking information. The stack-frame base pointer (contained in bp/fp register, the software can use general purpose register R15 as bp/fp) identifies a fixed reference point within the stack frame for the called procedure. To use the stack-frame base pointer, the called procedure typically copies the contents of the SP register into the bp/fp register prior to pushing any local variables on the stack. The stack-frame base pointer then permits easy access to data structures passed on the stack, to the return instruction pointer, and to local variables added to the stack by the called procedure.
Return instruction pointer: Prior to branching to the first instruction of the called procedure, the CALL instruction pushes the address in the PC register onto the current stack. This address is then called the return-instruction pointer and it points to the instruction where execution of the calling procedure should resume following a return from the called procedure. Upon returning from a called procedure, the RET instruction pops the return-instruction pointer from the stack back into the PC register. Execution of the calling procedure then resumes.
The processor does not keep track of the location of the return-instruction pointer. It is thus up to the programmer to insure that stack pointer is pointing to the return-instruction pointer on the stack, prior to issuing a RET instruction. A common way to reset the stack pointer to the point to the return-instruction pointer is to move the contents of the BP register into the sp register. If the bp/fp register is loaded with the stack pointer immediately following a procedure call, it should point to the return-instruction pointer on the stack.
The processor does not require that the return instruction pointer point back to the calling procedure. Prior to executing the RET instruction; the return-instruction pointer can be manipulated in software to point to any address in the memory. Performing such an operation, however, should be undertaken very cautiously, using only well defined code entry points.
7 Interrupts and Exceptions
The processor provides two mechanisms for interrupting program execution, interrupts and exceptions:
An interrupt is an asynchronous event that is typically triggered by an I/O device.
An exception is a synchronous event that is generated when the processor detects one or more predefined conditions while executing an instruction.
The processor responds to interrupts and exceptions in essentially the same way. When an interrupt or exception is signaled, the processor halts execution of the current program and switches to a handler procedure that has been written specifically to handle the interrupt or exception condition. The processor responds to an interrupt or exception with an implicit call to an interrupt or exception handler. The processor uses the interrupt or exception vector number as an index into an interrupt vector table. There are total 16 interrupt which separated by 8-bytes, the application can write exception/interrupt handler procedures in these locations or may jump to handler located at other memory locations.
The HPC-16 Architecture defines 5 predefined interrupts and exceptions and 11 user defined interrupts, which are associated with entries in the IVT. Each interrupt and exception in the IVT is identified with a number, called a vector. Table 4.1 lists the interrupts and exceptions with entries in the IVT and their respective vector numbers. Vectors 0 through 4 are the predefined exceptions, and vectors 5 through 15 are the user-defined interrupts, called maskable interrupts.
When the processor detects an interrupt or exception, it executes an implicit call to a handler procedure. The processor performs following actions when calling an interrupt or exception handler:
Pushes the current contents of the FLAGS, and PC registers respectively on the stack.
Loads the new program counter value with 8 * vector no.
Clears the IF flag in the FLAGS register
Begins execution of the handler procedure
A return from an interrupt or exception handler is initiated with the IRET instruction. The IRET instruction is similar to the far RET instruction, except that it also restores the contents of the FLAGS register for the interrupted procedure.
Restores the PC registers to their values prior to the interrupt or exception.
Restores the FLAGS register
Increments the stack pointer appropriately
Resumes execution of the interrupted procedure
Table: 7.1 Interrupt Vector Locations
Vector No.DescriptionSourceMemory Location,0OverflowINTO instruction0000h1Invalid instructionReserved Opcode0008h2Alignment errorAny memory reference0010h3Stack ErrorStack misalignment0018h4Double faultStack misalignment while executing maskable interrupt or during invalid instruction, alignment error 0020h5 15Maskable InterruptsExternal interrupt from INTR pin or INT n instruction0028h - 0078h
7.1 Invalid Instruction
This exception is raise when instruction contains invaild/reserved opcode, subop fields.
7.2 Alignment Exception
All the 16-bit word data or instruction, should be aligned on even address (i.e contain zero in least significant bit). Accessing misaligned word will cause this interrupt. However this instruction will not be raised, in case of lbzx/lbsx/sb instruction.
7.3 Stack Error Exception
If the stack contains odd address, for this exception CPU behavior is changed, CPU internally save offending SP content, then SP is asynchronously set to predefined value (0x0000). CPU pushes old SP value, FLAGS and PC and jump to Stack Exception vector location.
Figure: 7.1 Stack Error Exception
7.4 Double Fault
It may also possible, that some interrupt or exception (other than stack error) occur. Now processor needs to push flags and PC but if at this point, SP contain invalid value then this exception will occur. In this exception like Stack error, CPU internally saves the invalid contents of SP then SP is asynchronously preset to predefined value (0x0000). CPU pushes old interrupt no, old SP value, FLAGS and PC, then jump to Double Fault Exception vector location.
Figure: 7.2 Double Fault
7.5 Hardware interrupt
The hardware interrupt is raised by asserting INTR_I pin of CPU. The INTR_I generating source is required to assert it continuously until it is not recognized. The CPU first inspect the IF status (i.e can be masked by software by clearing IF) before checking INTR_I. Before pushing the FLAGS and PC, it generates a special read cycle to get the vector no. from slave device. In this read cycle IACK_CYC_O pin is asserted by CPU to indicate that it is special read cycle. The slave is suppose to put 4-bit interrupt number on databus(11..8), and deassert the INTR_I pin.
7.6 Software Interrupt
The software interrupt is generated by INT n and INTO instructions. The IF is not checked. The INT n and INTO allow a program or task to explicitly call an interrupt or exception handler. The INT n instruction uses an interrupt vector as an argument, which allows a program to call any interrupt handler.
The INTO instruction explicitly calls the overflow exception handler if the overflow flag (OF) in the FLAGS register is set. The OF flag indicates overflow on arithmetic instructions, but it does not automatically raise an overflow exception. An overflow exception can only be raised explicitly in either of the following ways:
Execute the INTO instruction.
Test the OF flag and execute the INT n instruction with an argument of 0 (the vector number of the overflow exception) if the flag is set.
8 HPC-16 Instructions
HPC-16 instruction set include several instructions, which shown in Appendix A. These instructions can divided into seven major categories, which are given below:
8.1 Data Transfer Instructions
The data transfer instructions move bytes, words both between memory and the processors registers and between registers. For the purpose of this discussion, these instructions are divided into subordinate subgroups that provide for:
General data movement
Stack manipulation
General Data Movement Instructions: The MOV (move) instruction transfer data between general-purpose registers (GPRs) and SP. The LI (load immediate) load constant 16-bit data into GPR and SP. The LD instruction load data from memory to GPR and ST instruction store data from GPR into memory. Separate mnemonics are provided for byte loading and storing, all the byte operands loaded from memory: LBSX sign extends the byte operand and load the result into GPR while LBZX zero extends the byte operand and then load result into GPR. SB stores the lower byte of GPR into memory.
Stack manipulation Instructions: The PUSH instruction decrements the stack pointer (contained in the SP register), then copies the source operand to the top of stack. It operates on GPR operands only. The POP instruction copies the word at the current top of stack (indicated by the SP register) to the location specified with the destination operand. It then increments the SP register to point to the new top of stack. The destination operand specifies a GPR only.
8.2 Binary Arithmetic Instructions
Binary arithmetic instructions operate on 16-bit numeric data encoded as signed or unsigned binary integers. For the purpose of this discussion, these instructions are divided subordinate subgroups of instructions that:
Add and subtract
Increment and decrement
Compare
Add and Subtract: The ADD (add integers), ADC (add integers with carry), SUB (subtract integers), and SBB (subtract integers with borrow) instructions perform addition and subtraction operations on signed or unsigned integer operands. The operands can be two GPRs, GPR-immediate or SP-immediate. The ADD instruction computes the sum of two integer operands. The ADC instruction computes the sum of two integer operands, plus 1 if the CF flag is set. This instruction is used to propagate a carry when adding numbers in stages. The SUB instruction computes the difference of two integer operands. The SBB instruction computes the difference of two integer operands, minus 1 if the CF flag is set. This instruction is used to propagate a borrow when subtracting numbers in stages. SP related instructions support only SUB and ADD operation.
Increment and Decrement Instructions: The INC (increment) and DEC (decrement) instructions add 1 to or subtract 1 from an unsigned integer operand (GPR) respectively, without affecting CF flag. A primary use of these instructions is for implementing counters.
Arithmetic Comparison: The CMP (compare) instruction computes the difference between two integer operands (two GPRs or GPR-immediate) and updates the OF, SF, ZF, AF, PF, and CF flags according to the result. The source operands are not modified, nor is the result saved. The CMP instruction is commonly used in conjunction with a Jcc (conditional jump) instruction.
8.3 Logical Instructions
The logical instructions AND, OR, XOR (exclusive or), and NOT perform the standard Boolean operations for which they are named. The AND, OR, and XOR instructions require two operands (two GPRs or GPR-immediate); the NOT instruction operates on a single operand (GPR). The TEST instruction performs a logical AND of two operands and sets the SF and ZF flags according to the results. The flags can then be tested by the conditional jump instructions. The TEST instruction differs from the AND instruction in that it does not alter either of the operands.
8.4 Shift and Rotate Instructions
The shift and rotate instructions rearrange the bits within an operand. For the purpose of this discussion, these instructions are further divided subordinate subgroups of instructions that:
Shift bits
Rotate bits
Shift Instructions: The SAL (shift arithmetic left), SHL (shift logical left), SAR (shift arithmetic right), SHR (shift logical right) instructions perform an arithmetic or logical shift of the bits in a word. The SAL and SHL instructions perform the same operation. They shift the source operand left by from 1 to 15 bit positions. Empty bit positions are cleared. The CF flag is loaded with the last bit shifted out of the operand. The SHR instruction shifts the source operand right by from 1 to 15 bit positions. As with the SHL/SAL instruction, the empty bit positions are cleared and the CF flag is loaded with the last bit shifted out of the operand. The SAR instruction shifts the source operand right by from 1 to 15 bit positions. This instruction differs from the SHR instruction in that it preserves the sign of the source operand by clearing empty bit positions if the operand is positive or setting the empty bits if the operand is negative. Again, the CF flag is loaded with the last bit shifted out of the operand.
Rotate Instructions: The ROL (rotate left), ROR (rotate right), RCL (rotate through carry left) and RCR (rotate through carry right) instructions rotate the bits in the destination operand out of one end and back through the other end. Unlike a shift, no bits are lost during a rotation. The rotate count can range from 0 to 15. The ROL instruction rotates the bits in the operand to the left (toward more significant bit locations). The ROR instruction rotates the operand right (toward less significant bit locations). The RCL instruction rotates the bits in the operand to the left, through the CF flag. This instruction treats the CF flag as a one-bit extension on the upper end of the operand. Each bit that exits from the most significant bit location of the operand moves into the CF flag. At the same time, the bit in the CF flag enters the least significant bit location of the operand. The RCR instruction rotates the bits in the operand to the right through the CF flag. For all the rotate instructions, the CF flag always contains the value of the last bit rotated out of the operand, even if the instruction does not use the CF flag as an extension of the operand. The value of this flag can then be tested by a conditional jump instruction (JC or JNC).
8.5 Control Transfer Instructions
The processor provides both conditional and unconditional control transfer instructions to direct the flow of program execution. Conditional transfers are taken only for specified states of the status flags in the FLAGS register. Unconditional control transfers are always executed. For the purpose of this discussion, these instructions are further divided subordinate subgroups that process:
Unconditional transfers
Conditional transfers
Software interrupts
Unconditional Transfer Instructions: The JMP, CALL and RET instructions transfer program control to another location (destination address) in the instruction stream. The destination can be any where within 64K addressable memory.
Jump instruction - The JMP (jump) instruction unconditionally transfers program control to a destination instruction. The transfer is one-way; that is, a return address is not saved. A destination operand specifies the address (the instruction pointer) of the destination instruction. The address can be a relative address or an absolute address.
A relative address is a displacement (offset) with respect to the address in the PC register. The destination address is formed by adding the displacement to the address in the PC register. The displacement is specified with a signed integer, present either as part of instruction (11 bit sign extended immediate constant) or present in GPR, allowing jumps either forward or backward in the instruction stream. An absolute address is the physical address of memory. Here, target address is value inside GPR. This value is directly copied into PC register.
Call and return instructions - The CALL (call procedure) and RET (return from procedure) instructions allow a jump from one procedure (or subroutine) to another and a subsequent jump back (return) to the calling procedure. The CALL instruction transfers program control from the current (or calling procedure) to another procedure (the called procedure). To allow a subsequent return to the calling procedure, the CALL instruction saves the current contents of the PC register on the stack before jumping to the called procedure. The PC register (prior to transferring program control) contains the address of the instruction following the CALL instruction. When this address is pushed on the stack, it is referred to as the return instruction pointer or return address. The address of the called procedure (the address of the first instruction in the procedure being jumped to) is specified in a CALL instruction the same way as it is in a JMP instruction. The address can be specified as a relative address or an absolute address.
The RET instruction transfers program control from the procedure currently being executed (the called procedure) back to the procedure that called it (the calling procedure). Transfer of control is accomplished by copying the return instruction pointer from the stack into the PC register. Program execution then continues with the instruction pointed to by the PC register.
Conditional transfer instructions: The conditional transfer instructions execute jumps that transfer program control to another instruction in the instruction stream if specified conditions are met. The conditions for control transfer are specified with a set of condition codes that define various states of the status flags (CF, ZF, OF and SF) in the FLAGS register. The Jcc (conditional) jump instructions transfer program control to a destination instruction if the conditions specified with the condition code (cc) associated with the instruction are satisfied. If the condition is not satisfied, execution continues with the instruction following the Jcc instruction. As with the JMP instruction, the transfer is one-way; that is, a return address is not saved.
Table: 8.1 Conditional Jump Instructions
Instruction MnemonicsCondition (Flags states)DescriptionUnsigned Conditional JumpsJA/JNBE(CF or ZF) = 0Above/ not below or equalJAE/JNBCF = 0Above or equal/ not belowJB/ JNAECF = 1Below/ not above or equalJBE/ JNA (CF or ZF) = 1Below or equal/ not aboveJCCF = 1CarryJE/JZZF = 1Equal / zeroJNCCF = 0Not carryJNE/ JNZZF = 0Not equal /not zeroSigned Conditional JumpsJG/ JNLE((SF xor OF) or ZF) = 0Greater/ not less or equal JGE/ JNL(SF xor OF) = 0Greater or equal/ not lessJL/JNGE(SF xor OF) = 1Less/ not greater or equal JLE/ JNG((SF xor OF) or ZF) = 1Less or equal / not greaterJNOOF = 0Not OverflowJNSSF = 0Not sign (non-negative)JOOF = 1OverflowJSSF = 1Sign (negative)
The target address is specified in a Jcc instruction as a relative address (7-bit sign extended immediate constant). Table shows the mnemonics for the Jcc instructions and the conditions being tested for each instruction. The condition code mnemonics are appended to the letter "J" to form the mnemonic for a Jcc instruction. The instructions are divided into two groups: unsigned and signed conditional jumps. These groups correspond to the results of operations performed on unsigned and signed integers respectively. Those instructions listed as pairs (for example, JA/JNBE) are alternate names for the same instruction.
Software Interrupt Instructions: The INT n (software interrupt) and INTO (interrupt on overflow) instructions allow a program to explicitly raise a specified interrupt or exception, which in turn causes the handler routine for the interrupt or exception to be called. The INT n instruction can raise any of the processors interrupts or exceptions by encoding the vector number or the interrupt or exception in the instruction. The contents of the FLAGS register are automatically stored on the stack along with the return instruction pointer when the processor services an interrupt. The IRET (return from interrupt) instruction returns program control from an interrupt handler to the interrupted procedure. The IRET instruction performs a similar operation to the RET instruction, except that it also restores the FLAGS register from the stack. The INTO instruction raises the overflow exception if the OF flag is set. If the flag is clear, execution continues without raising the exception. This instruction allows software to access the overflow exception handler explicitly to check for overflow conditions.
8.6 Flag Control Instructions
The Flag Control instructions allow the state of selected flags in the FLAGS register to be read or modified. For the purpose of this discussion, these instructions are further divided subordinate subgroups of instructions that manipulate:
Carry flag
The FLAGS register
Interrupt flag
Carry Flag Instructions: The STC (set carry flag), CLC (clear carry flag), and CMC (complement carry flag) instructions allow the CF flags in the FLAGS register to be modified directly. They are typically used to initialize the CF flag to a known state before an instruction that uses the flag in an operation is executed. They are also used in conjunction with the rotate-with-carry instructions (RCL and RCR).
FLAGS Transfer Instructions: The PUSHF (push flags) and POPF (pop flags) instructions copy the flags in the FLAGS register to and from the stack. The PUSHF pushes the FLAGS register onto the stack. The POPF instruction pops a word from the stack into the FLAGS register.
Interrupt Flag Instructions: The STI (set interrupt flag) and CTI (clear interrupt flag) instructions allow the interrupt IF flag in the FLAGS register to be modified directly.
8.7 Miscellaneous Instructions
The NOP instruction increments the PC register to point at the next instruction, but affect nothing else. HLT instruction stops further instruction execution, set the interrupt flag and places the processor in a HALTED state. An enabled interrupt or the RESET signal will resume execution. If an interrupt is used to resume execution after a HLT instruction, the saved instruction pointer (PC) points to the instruction following the HLT instruction.
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% ' ( 7 0 k N O Q { V v ) I 3 C X _ [ \ z { ! " " O# P# H% \% G& \& ' ' 2) H) ) ) * * +* + + , , . . / / 1 1 $2 92 3 3 3 13 C3 _4 i4 &5 (5 *5 >5 ?5 7 7 7 8 c8 d8 $9 B9 {9 9 9 : : ]: : : : ; ; > > A A ,C -C D D E oE F F H H J J pK qK K K (L RL SL FM GM M M M N
N 6N AN MN TN eN fN hN qN N N N N N N N N N N N N N N N O O O O O O O O O O O O O O P ZP rP rQ Q R R R R R T T T T T W &W XX YX Y Y JZ `Z [ "[ \ "\ 5\ 6\ z^ {^ P` s` Oa `a xa a d d e e >g Wg i i bj mj yj zj n n us s !u 9u Ou cu du Kv Lv w w y y } } W X X Y ۂ ܂
7 8 A H b c m | Ã ǃ ك ! 9 U V _ o Ʉ " : ; > E N O R Y i j k ۇ ܇ 6 T D O b q r ѐ ʒ ˒ ̒ ϒ 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p 0 0 p 0 0 p 0 0 p 0 0 p 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 0 { 0 0 V ( 0 V 0 ) 0 ) 0 ) 0 ) ( 0 V 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C ( 0 V 0 " 0 " 0 " ( 0 V 0 H% 0 0 G& 0 G& 0 ' 0 G& 0 2) 0 2) 0 2) 0 2) 0 G& 0 * 0 * 0 * 0 * 0 * 0 0 . 0 . 0 / 0 . 0 1 0 0 $2 0 $2 0 $2 0 $2 0 0 13 0 13 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 13 0 $9 0 $9 0 $9 0 $9 0 8 0 8 0 8 0 8 0 2 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 jO 0 D 0 O 0 D 0 P 0 P 0 P 0 P 0 D 0 =R 0 =R 0 =R 0 =R 0 D 0 5 ?5 7 7 7 8 c8 d8 $9 B9 {9 9 9 : : ]: : : : ; ; > > A A ,C -C D D E oE F F H H J J pK qK K K (L RL SL FM GM M M M N
N 6N AN MN TN eN fN hN qN N N N N N N N N N N N N N N N O O O O O O O O O O O O O O P ZP rP rQ Q R R R R R T T T T T W &W XX YX Y Y JZ `Z [ "[ \ "\ 5\ 6\ z^ {^ P` s` Oa `a xa a d d e e >g Wg i i bj mj yj zj n n us s !u 9u Ou cu du Kv Lv w w y y } } W X Y ۂ ܂
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7 8 A H b c m | Ã ǃ ك ! 9 U V _ o Ʉ " : ; > E N O R Y i j k ۇ ܇ 6 T D O b q r ѐ ʒ ˒ ̒ ϒ 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p 0 0 p 0 0 p 0 0 p 0 0 p 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 0 { 0 0 V ( 0 V 0 ) 0 ) 0 ) 0 ) ( 0 V 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C 0 C ( 0 V 0 " 0 " 0 " ( 0 V 0 H% 0 0 G& 0 G& 0 ' 0 G& 0 2) 0 2) 0 2) 0 2) 0 G& 0 * 0 * 0 * 0 * 0 * 0 0 . 0 . 0 / 0 . 0 1 0 0 $2 0 $2 0 $2 0 $2 0 0 13 0 13 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 13 0 $9 0 $9 0 $9 0 $9 0 8 0 8 0 8 0 8 0 2 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 ]: 0 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 jO 0 D 0 O 0 D 0 P 0 P 0 P 0 P 0 D 0 =R 0 =R 0 =R 0 =R 0 D 0 5 ?5 7 7 7 8 c8 d8 $9 B9 {9 9 9 : : ]: : : : ; ; > > A A ,C -C D D E oE F F H H J J pK qK K K (L RL SL FM GM M M M N
N 6N AN MN TN eN fN hN qN N N N N N N N N N N N N N N N O O O O O O O O O O O O O O P ZP rP rQ Q R R R R R T T T T T W &W XX YX Y Y JZ `Z [ "[ \ "\ 5\ 6\ z^ {^ P` s` Oa `a xa a d d e e >g Wg i i bj mj yj zj n n us s !u 9u Ou cu du Kv Lv w w y y } } W X Y ۂ ܂
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Title , 8 @ _PID_HLINKS A 6 _ T o c 1 1 3 4 7 9 3 2 1 6 _ T o c 1 1 3 4 7 9 3 2 0 6 _ T o c 1 1 3 4 7 9 3 1 9 6 _ T o c 1 1 3 4 7 9 3 1 8 6 _ T o c 1 1 3 4 7 9 3 1 7 6 _ T o c 1 1 3 4 7 9 3 1 6 6 _ T o c 1 1 3 4 7 9 3 1 5 6 _ T o c 1 1 3 4 7 9 3 1 4 6 _ T o c 1 1 3 4 7 9 3 1 3 6 _ T o c 1 1 3 4 7 9 3 1 2 6 _ T o c 1 1 3 4 7 9 3 1 1 6 _ T o c 1 1 3 4 7 9 3 1 0 6 _ T o c 1 1 3 4 7 9 3 0 9 6 _ T o c 1 1 3 4 7 9 3 0 8 6 _ T o c 1 1 3 4 7 9 3 0 7 6 _ T o c 1 1 3 4 7 9 3 0 6 6 _ T o c 1 1 3 4 7 9 3 0 5 6 z _ T o c 1 1 3 4 7 9 3 0 4 6 t _ T o c 1 1 3 4 7 9 3 0 3 6 n _ T o c 1 1 3 4 7 9 3 0 2 6 h _ T o c 1 1 3 4 7 9 3 0 1 6 b _ T o c 1 1 3 4 7 9 3 0 0 7 \ _ T o c 1 1 3 4 7 9 2 9 9 7 V _ T o c 1 1 3 4 7 9 2 9 8 7 P _ T o c 1 1 3 4 7 9 2 9 7 7 J _ T o c 1 1 3 4 7 9 2 9 6 7 D _ T o c 1 1 3 4 7 9 2 9 5 7 > _ T o c 1 1 3 4 7 9 2 9 4 7 8 _ T o c 1 1 3 4 7 9 2 9 3 7 2 _ T o c 1 1 3 4 7 9 2 9 2 7 , _ T o c 1 1 3 4 7 9 2 9 1 7 & _ T o c 1 1 3 4 7 9 2 9 0 7 _ T o c 1 1 3 4 7 9 2 8 9 7 _ T o c 1 1 3 4 7 9 2 8 8 7 _ T o c 1 1 3 4 7 9 2 8 7 7 _ T o c 1 1 3 4 7 9 2 8 6 7 _ T o c 1 1 3 4 7 9 2 8 5 7 _ T o c 1 1 3 4 7 9 2 8 4
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Title , 8 @ _PID_HLINKS A 6 _ T o c 1 1 3 4 7 9 3 2 1 6 _ T o c 1 1 3 4 7 9 3 2 0 6 _ T o c 1 1 3 4 7 9 3 1 9 6 _ T o c 1 1 3 4 7 9 3 1 8 6 _ T o c 1 1 3 4 7 9 3 1 7 6 _ T o c 1 1 3 4 7 9 3 1 6 6 _ T o c 1 1 3 4 7 9 3 1 5 6 _ T o c 1 1 3 4 7 9 3 1 4 6 _ T o c 1 1 3 4 7 9 3 1 3 6 _ T o c 1 1 3 4 7 9 3 1 2 6 _ T o c 1 1 3 4 7 9 3 1 1 6 _ T o c 1 1 3 4 7 9 3 1 0 6 _ T o c 1 1 3 4 7 9 3 0 9 6 _ T o c 1 1 3 4 7 9 3 0 8 6 _ T o c 1 1 3 4 7 9 3 0 7 6 _ T o c 1 1 3 4 7 9 3 0 6 6 _ T o c 1 1 3 4 7 9 3 0 5 6 z _ T o c 1 1 3 4 7 9 3 0 4 6 t _ T o c 1 1 3 4 7 9 3 0 3 6 n _ T o c 1 1 3 4 7 9 3 0 2 6 h _ T o c 1 1 3 4 7 9 3 0 1 6 b _ T o c 1 1 3 4 7 9 3 0 0 7 \ _ T o c 1 1 3 4 7 9 2 9 9 7 V _ T o c 1 1 3 4 7 9 2 9 8 7 P _ T o c 1 1 3 4 7 9 2 9 7 7 J _ T o c 1 1 3 4 7 9 2 9 6 7 D _ T o c 1 1 3 4 7 9 2 9 5 7 > _ T o c 1 1 3 4 7 9 2 9 4 7 8 _ T o c 1 1 3 4 7 9 2 9 3 7 2 _ T o c 1 1 3 4 7 9 2 9 2 7 , _ T o c 1 1 3 4 7 9 2 9 1 7 & _ T o c 1 1 3 4 7 9 2 9 0 7 _ T o c 1 1 3 4 7 9 2 8 9 7 _ T o c 1 1 3 4 7 9 2 8 8 7 _ T o c 1 1 3 4 7 9 2 8 7 7 _ T o c 1 1 3 4 7 9 2 8 6 7 _ T o c 1 1 3 4 7 9 2 8 5 7 _ T o c 1 1 3 4 7 9 2 8 4
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