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HPC-16 Instruction Reference Manual





M. Umair Siddiqui

Change Log
DateDescriptionAuthorsBefore ReleaseInitial DocumentM.Umair Siddiqui Before ReleaseFormatting & editing Jawwad AsifSep-03, 2005First ReleaseM. Umair Siddiqui
Table of Contents
 TOC \o "1-3" \h \z \u  HYPERLINK \l "_Toc125539112" HPC-16 Instruction Reference Manual	 PAGEREF _Toc125539112 \h i
 HYPERLINK \l "_Toc125539113" Change Log	 PAGEREF _Toc125539113 \h ii
 HYPERLINK \l "_Toc125539114" Table of Contents	 PAGEREF _Toc125539114 \h iii
 HYPERLINK \l "_Toc125539115" Instruction set reference	 PAGEREF _Toc125539115 \h 1
 HYPERLINK \l "_Toc125539116" MOVE	 PAGEREF _Toc125539116 \h 1
 HYPERLINK \l "_Toc125539117" MOV/COPY (register operand)	 PAGEREF _Toc125539117 \h 1
 HYPERLINK \l "_Toc125539118" Move/Copy (to stack pointer from reg)	 PAGEREF _Toc125539118 \h 1
 HYPERLINK \l "_Toc125539119" Move/Copy (to reg from stack pointer)	 PAGEREF _Toc125539119 \h 1
 HYPERLINK \l "_Toc125539120" LOAD WORD	 PAGEREF _Toc125539120 \h 2
 HYPERLINK \l "_Toc125539121" Load word from memory (register indirect mode)	 PAGEREF _Toc125539121 \h 2
 HYPERLINK \l "_Toc125539122" Load word from memory (register indirect + imm16)	 PAGEREF _Toc125539122 \h 2
 HYPERLINK \l "_Toc125539123" Load word from memory (using sp)	 PAGEREF _Toc125539123 \h 2
 HYPERLINK \l "_Toc125539124" Load word from memory (sp + imm16)	 PAGEREF _Toc125539124 \h 3
 HYPERLINK \l "_Toc125539125" STORE WORD	 PAGEREF _Toc125539125 \h 3
 HYPERLINK \l "_Toc125539126" Store word to memory (register indirect mode)	 PAGEREF _Toc125539126 \h 3
 HYPERLINK \l "_Toc125539127" Store word to memory (register indirect + imm16)	 PAGEREF _Toc125539127 \h 4
 HYPERLINK \l "_Toc125539128" Store word to memory (using sp)	 PAGEREF _Toc125539128 \h 4
 HYPERLINK \l "_Toc125539129" Store word to memory (sp + imm16)	 PAGEREF _Toc125539129 \h 4
 HYPERLINK \l "_Toc125539130" LOAD BYTE	 PAGEREF _Toc125539130 \h 5
 HYPERLINK \l "_Toc125539131" Load Byte from memory with zero ext (register indirect mode):	 PAGEREF _Toc125539131 \h 5
 HYPERLINK \l "_Toc125539132" Load Byte from memory with zero ext (register indirect + imm16):	 PAGEREF _Toc125539132 \h 5
 HYPERLINK \l "_Toc125539133" Load byte from memory with sign ext (register indirect mode):	 PAGEREF _Toc125539133 \h 5
 HYPERLINK \l "_Toc125539134" Load byte from memory with sign ext (register indirect + displacement mode)	 PAGEREF _Toc125539134 \h 6
 HYPERLINK \l "_Toc125539135" STORE BYTE	 PAGEREF _Toc125539135 \h 6
 HYPERLINK \l "_Toc125539136" Store byte to memory (register indirect mode)	 PAGEREF _Toc125539136 \h 6
 HYPERLINK \l "_Toc125539137" Store byte to memory (register indirect + imm16)	 PAGEREF _Toc125539137 \h 7
 HYPERLINK \l "_Toc125539138" LOAD IMMIDIATE	 PAGEREF _Toc125539138 \h 7
 HYPERLINK \l "_Toc125539139" Load 16-bit immediate value (constant) to register from memory	 PAGEREF _Toc125539139 \h 7
 HYPERLINK \l "_Toc125539140" Load 16-bit immediate value (constant) to sp from memory	 PAGEREF _Toc125539140 \h 7
 HYPERLINK \l "_Toc125539141" INC/DEC	 PAGEREF _Toc125539141 \h 8
 HYPERLINK \l "_Toc125539142" Increment (register operand)	 PAGEREF _Toc125539142 \h 8
 HYPERLINK \l "_Toc125539143" Decrement (register operand)	 PAGEREF _Toc125539143 \h 8
 HYPERLINK \l "_Toc125539144" ALU OPERATIONS	 PAGEREF _Toc125539144 \h 8
 HYPERLINK \l "_Toc125539145" Subtract (register operands)	 PAGEREF _Toc125539145 \h 8
 HYPERLINK \l "_Toc125539146" And (register operands)	 PAGEREF _Toc125539146 \h 9
 HYPERLINK \l "_Toc125539147" Add (register operands)	 PAGEREF _Toc125539147 \h 9
 HYPERLINK \l "_Toc125539148" Add with carry (register operands)	 PAGEREF _Toc125539148 \h 9
 HYPERLINK \l "_Toc125539149" Subtract with borrow (register operands)	 PAGEREF _Toc125539149 \h 10
 HYPERLINK \l "_Toc125539150" Logical inclusive or (register operands)	 PAGEREF _Toc125539150 \h 10
 HYPERLINK \l "_Toc125539151" Exclusive or (register operands)	 PAGEREF _Toc125539151 \h 10
 HYPERLINK \l "_Toc125539152" Logical not (register operand)	 PAGEREF _Toc125539152 \h 11
 HYPERLINK \l "_Toc125539153" ALU OPERATIONS IMMIDIATE	 PAGEREF _Toc125539153 \h 11
 HYPERLINK \l "_Toc125539154" Subtract (register and immediate operands)	 PAGEREF _Toc125539154 \h 11
 HYPERLINK \l "_Toc125539155" logical and (register and immediate operands)	 PAGEREF _Toc125539155 \h 11
 HYPERLINK \l "_Toc125539156" Addition (register and immediate operands)	 PAGEREF _Toc125539156 \h 12
 HYPERLINK \l "_Toc125539157" Add with carry (register and immediate operands)	 PAGEREF _Toc125539157 \h 12
 HYPERLINK \l "_Toc125539158" Subtract with borrow (register and immediate operands)	 PAGEREF _Toc125539158 \h 12
 HYPERLINK \l "_Toc125539159" Logical inclusive or (register and immediate operands)	 PAGEREF _Toc125539159 \h 13
 HYPERLINK \l "_Toc125539160" Exclusive or (register and immediate operands)	 PAGEREF _Toc125539160 \h 13
 HYPERLINK \l "_Toc125539161" ADD/SUB-I SP	 PAGEREF _Toc125539161 \h 13
 HYPERLINK \l "_Toc125539162" Addition (Stack pointer and immediate operands)	 PAGEREF _Toc125539162 \h 13
 HYPERLINK \l "_Toc125539163" Subtract (Stack operation and immediate operands)	 PAGEREF _Toc125539163 \h 14
 HYPERLINK \l "_Toc125539164" FLAG OPERATION	 PAGEREF _Toc125539164 \h 14
 HYPERLINK \l "_Toc125539165" Compare two register operands	 PAGEREF _Toc125539165 \h 14
 HYPERLINK \l "_Toc125539166" Logical Comparison between register operands	 PAGEREF _Toc125539166 \h 14
 HYPERLINK \l "_Toc125539167" FLAG OPERATION IMMIDIATE	 PAGEREF _Toc125539167 \h 15
 HYPERLINK \l "_Toc125539168" Compare (register and immediate operands)	 PAGEREF _Toc125539168 \h 15
 HYPERLINK \l "_Toc125539169" Logical Compare (register and immediate operands)	 PAGEREF _Toc125539169 \h 15
 HYPERLINK \l "_Toc125539170" SHIFT OPERATION	 PAGEREF _Toc125539170 \h 16
 HYPERLINK \l "_Toc125539171" Shift logical left (register operand)	 PAGEREF _Toc125539171 \h 16
 HYPERLINK \l "_Toc125539172" Shift logical right (register operand)	 PAGEREF _Toc125539172 \h 16
 HYPERLINK \l "_Toc125539173" Shift arithmetic left (register operand)	 PAGEREF _Toc125539173 \h 16
 HYPERLINK \l "_Toc125539174" Shift arithmetic right (register operand)	 PAGEREF _Toc125539174 \h 17
 HYPERLINK \l "_Toc125539175" Rotate left (register operands)	 PAGEREF _Toc125539175 \h 17
 HYPERLINK \l "_Toc125539176" Rotate right (register operand)	 PAGEREF _Toc125539176 \h 18
 HYPERLINK \l "_Toc125539177" Rotate carry left (register operand)	 PAGEREF _Toc125539177 \h 18
 HYPERLINK \l "_Toc125539178" Rotate carry right (register operand)	 PAGEREF _Toc125539178 \h 18
 HYPERLINK \l "_Toc125539179" SHIFT IMMEDIATE	 PAGEREF _Toc125539179 \h 19
 HYPERLINK \l "_Toc125539180" Shift logical left (imm4 operand)	 PAGEREF _Toc125539180 \h 19
 HYPERLINK \l "_Toc125539181" Shift logical right (imm4 operand)	 PAGEREF _Toc125539181 \h 19
 HYPERLINK \l "_Toc125539182" Shift arithmetic left (imm4 operand)	 PAGEREF _Toc125539182 \h 19
 HYPERLINK \l "_Toc125539183" Shift arithmetic right (imm4 operand)	 PAGEREF _Toc125539183 \h 20
 HYPERLINK \l "_Toc125539184" Rotate left (imm4 operand)	 PAGEREF _Toc125539184 \h 20
 HYPERLINK \l "_Toc125539185" Rotate right (imm4 operand)	 PAGEREF _Toc125539185 \h 21
 HYPERLINK \l "_Toc125539186" Rotate carry left (imm4 operand)	 PAGEREF _Toc125539186 \h 21
 HYPERLINK \l "_Toc125539187" Rotate carry right (imm4 operand)	 PAGEREF _Toc125539187 \h 21
 HYPERLINK \l "_Toc125539188" STACK	 PAGEREF _Toc125539188 \h 22
 HYPERLINK \l "_Toc125539189" Push register onto the stack	 PAGEREF _Toc125539189 \h 22
 HYPERLINK \l "_Toc125539190" Push FLAGS onto the stack	 PAGEREF _Toc125539190 \h 22
 HYPERLINK \l "_Toc125539191" Pop word off stack to destination register	 PAGEREF _Toc125539191 \h 22
 HYPERLINK \l "_Toc125539192" Pop word off stack to FLAGS	 PAGEREF _Toc125539192 \h 23
 HYPERLINK \l "_Toc125539193" CALL	 PAGEREF _Toc125539193 \h 23
 HYPERLINK \l "_Toc125539194" Procedure Call (absolute address)	 PAGEREF _Toc125539194 \h 23
 HYPERLINK \l "_Toc125539195" Procedure Call (relative address)	 PAGEREF _Toc125539195 \h 24
 HYPERLINK \l "_Toc125539196" Procedure Call (relative call with imm11)	 PAGEREF _Toc125539196 \h 24
 HYPERLINK \l "_Toc125539197" RETURN	 PAGEREF _Toc125539197 \h 24
 HYPERLINK \l "_Toc125539198" FLAG OPERATIONS	 PAGEREF _Toc125539198 \h 25
 HYPERLINK \l "_Toc125539199" CLC : Clear Carry	 PAGEREF _Toc125539199 \h 25
 HYPERLINK \l "_Toc125539200" STC : Set Carry Flag	 PAGEREF _Toc125539200 \h 25
 HYPERLINK \l "_Toc125539201" CMC : Complement Carry Flag	 PAGEREF _Toc125539201 \h 25
 HYPERLINK \l "_Toc125539202" CLI : Clear Interrupt Flag	 PAGEREF _Toc125539202 \h 26
 HYPERLINK \l "_Toc125539203" STI : Set Interrupt flag	 PAGEREF _Toc125539203 \h 26
 HYPERLINK \l "_Toc125539204" JMP	 PAGEREF _Toc125539204 \h 26
 HYPERLINK \l "_Toc125539205" JMP (absolute address)	 PAGEREF _Toc125539205 \h 26
 HYPERLINK \l "_Toc125539206" JMP (relative address)	 PAGEREF _Toc125539206 \h 27
 HYPERLINK \l "_Toc125539207" JMP (relative call with imm11)	 PAGEREF _Toc125539207 \h 27
 HYPERLINK \l "_Toc125539208" JCC (conditional)	 PAGEREF _Toc125539208 \h 27
 HYPERLINK \l "_Toc125539209" INT	 PAGEREF _Toc125539209 \h 28
 HYPERLINK \l "_Toc125539210" INTO : Interrupt overflow	 PAGEREF _Toc125539210 \h 28
 HYPERLINK \l "_Toc125539211" INTERRUPT RETURN	 PAGEREF _Toc125539211 \h 29
 HYPERLINK \l "_Toc125539212" NO OPERATION (NOP)	 PAGEREF _Toc125539212 \h 29
 HYPERLINK \l "_Toc125539213" HALT	 PAGEREF _Toc125539213 \h 29

Instruction set reference

MOVE

MOV/COPY (register operand)

Format		: MOV rn, rm

Operation	:  rn = rm

Flags Affected: none

Encoding	: 
00000001nnnnmmmm

Description: Copies the source register (rm) to destination register (rn)

Move/Copy (to stack pointer from reg)

Format		: MOV sp, mmmm

Operation	:  SP = rm

Flags Affected: none

Encoding	: 
00000010xxxxmmmm

Description: Copies the source register (rm) to stack pointer (sp)

Move/Copy (to reg from stack pointer)

Format		: MOV nnnn, sp

Operation	:  rn = sp

Flags Affected: none

Encoding	:
00000100nnnnxxxx
Description: Copies the stack pointer (sp) to destination register (rn)


LOAD WORD

Load word from memory (register indirect mode)

Format		: LD rn, (rb)

Operation 	:  rn = Memory[rb]

Flags Affected:  none

Encoding	: 
00001000nnnnbbbb
Exceptions: Alignment exception will be raised in case of accessing misaligned word. 

Description: load the word data from memory at address present in "rb" register.


Load word from memory (register indirect + imm16)

Format		: LD rn, (rb + 0xhhhh)

Operation 	:  rn = Memory[rb + 0xhhhh]

Flags Affected:  none

Encoding	: 
00001001nnnnbbbb imm16

Exceptions: Alignment exception will be raised in case of accessing misaligned word. 

Description: Calculate the effective address by adding the content of "rb" register and 16-bit signed constant and load the word data from memory present at effective address. 


Load word from memory (using sp)

Format		: LD rn, (sp)

Operation 	:  rn = Memory[sp]

Flags Affected:  none

Encoding	: 
00001010nnnnxxxx
Description: load the word data from memory at address present in "sp" stack pointer.


Load word from memory (sp + imm16)

Format		: LD rn, (sp + 0xhhhh)

Operation 	:  rn = Memory[sp + 0xhhhh]

Flags Affected:  none

Encoding	: 
00001100nnnnxxxx  imm16
Description: Calculate the effective address by adding the content of "sp" stack pointer and 16-bit signed constant and load the word data from memory present at effective address. 



STORE WORD

Store word to memory (register indirect mode)

Format		: ST rn, (rb)

Operation 	: Memory[rb] = rn

Flags Affected: none

Encoding	: 
00010000nnnnbbbb
Exception:  Alignment exception will be raised in case of accessing misaligned word

Description: store the register content into memory at address present in "rb" register

Store word to memory (register indirect + imm16)

Format		: ST rn, (rb + imm16)

Operation 	: Memory[rb + imm16] = rn

Flags Affected: none

Encoding	: 
00010001nnnnbbbb  imm16
Exceptions: Alignment exception will be raised in case of accessing misaligned word

Description: Calculate the effective address by adding the content of "rb" register and 16-bit signed constant and store the register content into memory at effective address. 

Store word to memory (using sp)

Format		: ST rn, (sp)

Operation 	: Memory[sp] = rn

Flags Affected: none

Encoding	: 
00010010nnnnxxxx
Exception:  Alignment exception will be raised in case of accessing misaligned word

Description: store the register content into memory at address present in "sp" stack pointer.

Store word to memory (sp + imm16)

Format		: ST rn, (sp + imm16)

Operation 	: Memory[sp + imm16] = rn

Flags Affected: none

Encoding	: 
00010100nnnnxxxx imm16
Exceptions: Alignment exception will be raised in case of accessing misaligned word

Description: Calculate the effective address by adding the content of "sp" stack pointer and 16-bit signed constant and store the register content into memory at effective address. 


LOAD BYTE

Load Byte from memory with zero ext (register indirect mode):

Format		: LBZX rn , (rb)

Operation 	: rn = zero ext( Memory[rb]) 

Flags Affected: none

Encoding	: 
00011000nnnnbbbb
Description: using the base address, load the lower byte of destination register with the content at the base address and fill the upper byte of destination register with all zeros.

Load Byte from memory with zero ext (register indirect + imm16):

Format		: LBZX rn , ( rb + imm16)

Operation 	: rn = zero ext( Memory[rb + imm16]) 

Flags Affected: none

Encoding	: 
00011100nnnnbbbb imm16
Description: Calculate the effective address by adding the content in base register with a 16-bit signed constant and load the lower byte of destination register with the content at the effective address and fill the upper byte of destination register with all zeros.

Load byte from memory with sign ext (register indirect mode):							
Format		: LBSX rn , (rb)

Operation 	:  rn = sign ext(Memory[rb])

Flags Affected:  none


Encoding	: 
00011001nnnnbbbb
Description: Using the base address load the lower byte of destination register with the content at the base address and fill the upper byte of destination register with the MSB of the lower byte.

Load byte from memory with sign ext (register indirect + displacement mode)							
Format		: LBSX rn , ( rb + imm16)

Operation 	:  rn = sign ext(Memory[ rb+ imm16])

Flags Affected:  none

Encoding	: 
00011101nnnnbbbb imm16
Description: Calculate the effective address by adding the value of base register with a 16-bit signed immediate value and load the lower byte of destination register with the content at the effective address and fill the upper byte of destination register with the MSB of the lower byte.

STORE BYTE

Store byte to memory (register indirect mode)					

Format		: SB rn, (rb)

Operation 	: Memory[ rb ] = rn

Flags Affected: none

Encoding	:    
00100001nnnnbbbb
Description     : Using the base address, store the lower byte of destination register at the location pointed by the base address.

Store byte to memory (register indirect + imm16)
					
Format		: SB rn, ( rb + imm16)

Operation 	: Memory[ rb + imm16] = rn

Flags Affected: none

Encoding	: 
00100010nnnnbbbb imm16
Description     : Calculate the effective address by adding the value of base register with a 16-bit signed immediate value and store the lower byte of destination register at the location pointed by the effective address.


LOAD IMMIDIATE

Load 16-bit immediate value (constant) to register from memory

Format		: LI rn , imm16

Operation	:  rn = imm16

Flags Affected : none

Encoding	: 
01001001Nnnnxxxx imm16
Description: Load immediate/constant 16-bit data to the destination register

Load 16-bit immediate value (constant) to sp from memory

Format		: LI sp , imm16

Operation	:  sp = imm16

Flags Affected : none

Encoding	: 
01001010xxxxxxxx imm16
Description: Load immediate/constant 16-bit data to the stack pointer.



INC/DEC

Increment (register operand)

Format		: INC rn

Operation	: rn = rn + 1

Flags Affected: CF is preserved while OF, SF, ZF are set according to result

Encoding 	: 
00101001nnnnxxxx
Description: Add 1 to destination register while preserving the state of CF. 

Decrement (register operand) 

Format		: DEC rn

Operation	:  rn = rn - 1 

Flags Affected: CF is preserved while OF, SF, ZF are set according to result

Encoding	: 
00101000nnnnxxxx
Description: Subtract 1 from destination register while preserving the state of CF. 

ALU OPERATIONS

Subtract (register operands)

Format		: SUB rn, rm

Operation 	: rn = rn  rm 

Flags Affected: OF, SF, ZF, CF are set according to result

Encoding	: 
00110000nnnnmmmm
Description: Subtract source register from destination register and store result in destination register

And (register operands)

Format		: AND rn, rm

Operation	:  rn = rn AND rm 

Flags Affected:  OF and CF cleared, SF and ZF are set according to result 

Encoding	: 
00110101nnnnmmmm
Description: Perform bitwise AND operation between destination register and source register and store the result in destination register.

Add (register operands)

Format		: ADD rn, rm

Operation	: rn = rm + rn

Flags Affected:   OF, SF, ZF and CF are affected according to result  

Encoding	: 
00110001nnnnmmmm
Description: Add destination register and source register, and store result in destination register

Add with carry (register operands)

Format		: ADC rn, rm

Operation	: rn = rn + rm + CF	              

Flags Affected:  OF, SF, ZF, CF are affected according to result 

Encoding	:  
00110011nnnnmmmm
Description	:  Add the destination register, source register and CF, and store result in destination register. ADC instruction is useful for multi word addition

Subtract with borrow (register operands)

Format		: SBB rn, rm

Operation	: rn = rn  (rm + CF)

Flags Affected :  OF, SF, ZF, CF affected according to result 

Encoding	:  
00110010nnnnmmmm
Description: Add the source register with CF and subtract the result from destination register, and store result in destination register. SBB is useful for multi word subtraction.

Logical inclusive or (register operands)

Format		: OR rn, rm

Operation	:  rn = rn OR rm

Flags Affected :  OF and CF are cleared, SF and ZF are set according to result 

Encoding	:  
00110110nnnnmmmm
Description: Perform bitwise OR operation between destination and source registers and store the result in destination register.  

Exclusive or (register operands)

Format		: XOR rn, rm

Operation	:  rn = rn XOR rm

Flags Affected:  OF, CF are cleared, ZF and SF set according to result 

Encoding	: 
00110111nnnnmmmm
Description: Perform bitwise XOR operation between destination and source registers and store the result in destination register.


Logical not (register operand)

Format		: NOT rn

Operation	:  rn = NOT (rn)

Flags Affected: none

Encoding	: 
00110100nnnnmmmm
Description: Performs bitwise-NOT operation on destination register (rn).

ALU OPERATIONS IMMIDIATE

Subtract (register and immediate operands)

Format		: SUB rn, imm16

Operation 	: rn = rn  imm16 

Flags Affected:  OF, SF, ZF, CF are set to according result 

Encoding	: 
01010000nnnnxxxx imm16
Description   : Subtract immediate 16-bit data from destination register and store the result in the destination registerrn.


logical and (register and immediate operands)

Format		: AND rn, imm16

Operation	: rn = rn AND imm16

Flags Affected:   OF and CF are cleared, ZF and SF are set according to result  

Encoding	: 
01010101nnnnxxxx imm16
Description:     Perform bitwise AND operation between rn and 16-bit constant and store result in rn.

Addition (register and immediate operands)

Format		: ADD rn, imm16

Operation	: rn  = rn + imm16

Flags Affected:  OF, SF, ZF, CF are affected according to result. 

Encoding	: 
01010001nnnnxxxx imm16

Description: Add content of rn and 16-bit constant and store rn

Add with carry (register and immediate operands)

Format		: ADC rn, imm16

Operation	:   rn = rn + imm16 + CF
	
Flags Affected:   OF, SF, ZF, CF are affected according to result 

Encoding	: 
01010011nnnnxxxx imm16
Description: Add the destination register, 16-bit constant and CF, and store result in destination register. ADC instruction is useful for multi word addition

Subtract with borrow (register and immediate operands)

Format		: SBB rn, imm16

Operation	:  rn = rn  (imm16 + CF)

Flags Affected: OF, SF, ZF, CF are set according to result 

Encoding	:  
01010010nnnnxxxx imm16
Description: Add the source register with CF and subtract the result from destination register, and store result in destination register. SBB is useful for multi word subtraction.

Logical inclusive or (register and immediate operands)

Format		: OR reg_dest, imm16

Operation	: reg_dest = reg_dest OR imm16 

Flags Affected:  OF, CF are cleared and SF, ZF set according to result 

Encoding	: 
01010110nnnnxxxx imm16
Description: Performs bitwise OR operation between content of reg_dest and 16-bit constant and store result in destination register.

Exclusive or (register and immediate operands)

Format		: XOR rn, imm16

Operation	: rn = rn XOR imm16

Flags Affected:   OF, CF are cleared and ZF, SF are set according to result 

Encoding	: 
01010111nnnnxxxx imm16
Description: Performs bitwise XOR operation between content of rn and 16-bit constant and store result in destination result 


ADD/SUB-I SP

Addition (Stack pointer and immediate operands)

Format		: ADD sp, imm16

Operation	: sp  = sp + imm16

Flags Affected:  OF, SF, ZF, CF are affected according to result. 

Encoding	:  
01101001xxxxxxxx imm16
Description: Add content of stack pointer sp and 16-bit constant and store sp.

Subtract (Stack operation and immediate operands)

Format		: SUB sp, imm16

Operation 	: sp = sp  imm16 

Flags Affected:  OF, SF, ZF, CF are set to according result 

Encoding	: 
01101000xxxxxxxx imm16

Description   : Subtract immediate 16-bit data from stack pointersp and store the result in the sp.


FLAG OPERATION

Compare two register operands

Format		: CMP rn, rm

Operation 	: temp = rn  rm
	ModifyStatusFlags;

Flags Affected: OF, SF, ZF, CF are set according 

Encoding   : 
01000000nnnnmmmm
Description: compare two register operands and set the status flags. Without affecting operands the comparison is performed by subtracting rn from rm and setting the status flags in same manner as the SUB instruction. 

Logical Comparison between register operands 

Format          : TEST rn, rm

Operation        : temp = rn AND rm
             ModifyStatusFlags

Flags Affected : OF, CF are cleared, SF and ZF are set according to result 

Encoding        : 
01000101nnnnmmmm
Description: Perform logical comparison between both register operands. Without affecting operands the comparison is performed by bitwise-AND operation between rn and rm and setting the status flags in same manner as the AND instruction. 


FLAG OPERATION IMMIDIATE

Compare (register and immediate operands)  

Format             : CMP rn, imm16

Operation      : temp = rn  imm16
    ModifyStatusFlags;

Flags Affected: OF, SF, ZF, CF are set according 

Encoding : 
01100000nnnnxxxx imm16
Description: compare register operand with 16-bit constant and set the status flags. Without affecting operands the comparison is performed by subtracting the constant from rn and setting the status flags in same manner as the SUB instruction. 

Logical Compare (register and immediate operands)

Format                : TEST rn, imm16

Operation     : temp = rn AND imm16
          ModifyStatusFlags

Flags Affected : OF, CF are cleared, SF and ZF are set according to result 

Encoding        : 
01100101nnnnxxxx imm16
Description: Perform logical comparison between register operand and 16-bit constant. Without affecting operands the comparison is performed by bitwise-AND operation between reg1 and constant and setting the status flags in same manner as the AND instruction. 


SHIFT OPERATION

Shift logical left (register operand)

Format          : SLL rn, rm
                                           
Operation      :  rn << rm
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
00111000 nnnnmmmm  	
Description: Shifts the bits in the destination register to the left by the number of bits specified in the rm register. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift logical right (register operand) 

Format		: SLR rn, rm

Operation	:  rn >>> rm

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding      : 
00111001nnnnmmmm
Description: Shifts the bits in the destination register to the right by the number of bits specified in the rm register. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic left (register operand) 
 
Format          : SAL rn, rm
                                           
Operation      :  rn << rm
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
00111010nnnnmmmm	
Description: Shifts the bits in the destination register to the left by the number of bits specified in the rm register. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic right (register operand)

Format		: SAR rn, rm

Operation	:  rn >>> rm

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding      : 
00111011nnnnmmmm
Description: Shifts the bits in the destination register to the right by the number of bits specified in the rm register. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit retained its original value. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Rotate left (register operands)

Format            : ROL rn , rm

Operation        : rotate_left(rn), rm times

Flags              : The CF flag contains the value of the bit shifted into it

Encoding   : 
00111100nnnnmmmm
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified in the rm register) toward more-significant bit positions, except for the most-significant bit, which is rotated to the least significant bit location and stores the result in the destination operand.

Rotate right (register operand)

Format               : ROR rn , rm

Operation        : rotate_right(rn), rm times

Flags Affected :  The CF flag contains the value of the bit shifted into it

Encoding     : 
00111101nnnnmmmm
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified in the rm register) toward less-significant bit positions, except for the least-significant bit, which is rotated to the most significant bit location and stores the result in the destination operand.

Rotate carry left (register operand)

Format          : RCL rn, rm

Operation : rotate_left_with_carry(rn), rm times

Flags Affected:  The CF flag contains the value of the bit shifted into it 

Encoding   : 
00111110nnnnmmmm
Description: The Instruction rotates the rnn to the left through CF resulting in the MSB being placed in the CF and old CF ended in the LSB. The rm defines the number of rotations.    

Rotate carry right (register operand)

Format             : RCR rn, rm

Operation : rotate_right_with_carry(rn), rm times

Flags Affected:   The CF flag contains the value of the bit shifted into it

Encoding  : 
00111111nnnnmmmm
Description: The Instruction rotates the rn to the right through CF resulting in the LSB being placed in the CF and old CF ended in the MSB. The rm defines the number of rotations

SHIFT IMMEDIATE

Shift logical left (imm4 operand)

Format            : SLL rn, imm(3:0)
                                             
Operation      :  rn << imm(3:0)
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
01011000nnnnimm(3..0)	
Description: Shifts the bits in the destination register to the left by the number of bits specified by the 4 bit immediate value. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift logical right (imm4 operand) 

Format		: SLR rn, imm(3:0)

Operation	:  rn >>> imm(3:0)

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding        : 
01011001nnnnimm(3..0)
Description: Shifts the bits in the destination register to the right by the number of bits specified by the 4 bit immediate value. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.
Shift arithmetic left (imm4 operand) 
 
Format          : SAL rn, imm(3:0)
                                             
Operation      :  rn << imm(3:0)
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
01011010nnnnimm(3..0)	
Description: Shifts the bits in the destination register to the left by the number of bits specified by the 4 bit immediate value. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic right (imm4 operand)

Format		: SAR rn, imm(3:0)

Operation	:  rn >>> imm(3:0)

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding        : 
01011011nnnnimm(3..0)
Description: Shifts the bits in the destination register to the right by the number of bits specified by the 4 bit immediate value. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit retained its original value. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.


Rotate left (imm4 operand)

Format           : ROL rn , imm(3:0)

Operation  : rotate_left(rn), imm times

Flags             : The CF flag contains the value of the bit shifted into it



Encoding : 
01011100nnnnimm(3..0)
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified by the 4 bit immediate value) toward more-significant bit positions, except for the most-significant bit, which is rotated to the least significant bit location and stores the result in the destination operand.


Rotate right (imm4 operand)

Format             : ROR rn , imm(3:0)

Operation  : rotate_right(rn), imm times

Flags Affected :  The CF flag contains the value of the bit shifted into it

Encoding    : 
01011101Nnnnimm(3..0)
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified by the 4 bit immediate value) toward less-significant bit positions, except for the least-significant bit, which is rotated to the most significant bit location and stores the result in the destination operand.

Rotate carry left (imm4 operand)

Format         : RCL rn, imm(3:0)

Operation   : rotate_left_with_carry(rn), imm times

Flags Affected:  The CF flag contains the value of the bit shifted into it 

Encoding  : 
01011110nnnnimm(3..0)
Description: The Instruction rotates the rn to the left through CF resulting in the MSB being placed in the CF and old CF ended in the LSB. The 4 bit immediate value defines the number of rotations.    

Rotate carry right (imm4 operand)

Format           : RCR rn, imm(3:0)

Operation   : rotate_right_with_carry(rn), imm times

Flags Affected:   The CF flag contains the value of the bit shifted into it

Encoding : 
01011111nnnnimm(3..0)
Description: The Instruction rotates the rn to the right through CF resulting in the LSB being placed in the CF and old CF ended in the MSB. The 4 bit immediate value defines the number of rotations


STACK

Push register onto the stack

Format            : PUSH rn

Operation    : SP = SP  2
  Memory[SP] = rn

Flags Affected:  none

Encoding        : 
01110000xxxxxxxx  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Decrement the stack pointer (SP) by 2 and then transfers the register content to the new top of the stack. 

Push FLAGS onto the stack

Format          : PUSHF
 
Operation     : SP = SP  2 
 Memory[SP] = FLAGS

Flags Affected:  none

Encoding     :  
01110001xxxxxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Decrement the SP by 2 and then transfers FLAGS register to the new top of the stack.

Pop word off stack to destination register

Format         : POP rn

Operation     :  rn = Memory[SP]
        SP = SP + 2

Flags Affected:  none

Encoding         : 
01110100xxxxxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: The content of the register `rn is replaced by the word at the top of stack and SP is incremented by 2. 

Pop word off stack to FLAGS

Format            : POPF

Operation       : FLAGS = Memory[SP]
     SP = SP + 2

Flags Affected:  All flags are affected (including interrupt flag) 

Encoding    : 
01110101xxxxxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Transfer the memory word into FLAGS register and increment the SP by 2.

CALL

Procedure Call (absolute address)

Format          : ACALL (rb)

Operation :  temp = rb 
     push( PC )
     PC = temp

Flags Affected:   none

Encoding  :    
01111001xxxxbbbb  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: The address of the next sequential instruction is pushed on to the stack and the control is transferred to the base address  

Procedure Call (relative address)

Format             : LCALL (rb)

Operation :  temp = rb                    
          push( PC )
     PC = PC + temp

Flags Affected:   none

Encoding     :    
01111010xxxxbbbb  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description:  PC will be added to temp and then the PC will be updated.


Procedure Call (relative call with imm11)

Format               : SCALL  imm11

Operation       :  temp = sign ext(imm11)                       
          push( PC )
     PC = PC + temp

Flags Affected:   none

Encoding     :    
10000imm(10..0)
 
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: 11-bit immediate value with sign extension will be loaded into PC

RETURN

Format              : RET

Operation        : pop(PC)

Flags Affected : none

Encoding      : 
10001xxxxxxxxxxx
Exception: stack alignment exception will be raised, if SP contains odd value

Description: Return control after the called procedure has been executed. PC is updated by popping one word from the stack

FLAG OPERATIONS

CLC : Clear Carry

Format  : CLC        

Operation        : CF = 0

Flags Affected : CF

Encoding : 
11000000xxxxXxxx
Description: Clear the carry flag

STC : Set Carry Flag

Format        : SLC

Operation        : CF = 1

Flags Affected:  CF

Encoding :  
11000001xxxxXxxx
Description: set the carry flag

CMC : Complement Carry Flag

Format  : SLC

Operation        : CF = NOT( CF )

Flags Affected:  CF

Encoding : 
11000010xxxxXxxx
Description: complement the carry flag


CLI : Clear Interrupt Flag

Format    : CLI

Operation        : IF = 0

Flags Affected:  IF

Encoding : 
11000100xxxxXxxx
Description: Clear the interrupt flag. As a result all the maskable external interrupts become disabled.  

STI : Set Interrupt flag
Format    : STI

Operation        : IF = 1

Flags Affected:  IF

Encoding : 
11000101xxxxxxxx
Description: set the interrupt flag, the processor begins responding to external, maskable interrupts 

JMP

JMP (absolute address)

Format            : AJMP (rb)

Operation  :  temp = rb 
     PC = temp

Flags Affected:   none

Encoding  :    
10101001xxxxbbbb  

Description: The control is transferred to the base address. 


JMP (relative address)

Format           : LJMP (rb)

Operation  :  temp = rb                    
           PC = PC+temp

Flags Affected:   none

Encoding      :    
10101010xxxxbbbb  

Description:  Pc will be added to temp and then the PC will be updated.


JMP (relative call with imm11)

Format         : SJMP  imm11

Operation        :  temp = sign ext(imm11)
         PC = PC + temp

Flags Affected:   none

Encoding     :    
10110imm(10..0)
 
Description: 11-bit immediate value with sign extension will be loaded into PC

JCC (conditional)

Format            : Jcc  imm(6..0)
Operation      :  if condition satisfied
              temp = sign ext (imm(6..0))
            PC = PC + temp

Flags Affected:   none

Encoding        :    
10111imm(6..4)tttnimm(3..0) 
Description: 7-bit immediate value with sign extension will be loaded into PC.

tttnmnemoniccondition`0000OOverflowOF = 1`0001NOno overflowOF = 0`0010B, NAEbelow, not above or equalCF = 1`0011NB, AEnot below, above or equalCF = 0`0100E, Zequal, zeroZF = 1`0101NE, NZnot equal, not zeroZF = 0`0110BE, NAbelow or equal, not aboveCF = 1 or ZF = 1`0111NBE, Anot below or equal, aboveCF = 0 and ZF = 0`1000SsignSF = 1`1001NSnot signSF = 0`1010`1011`1100L, NGEless than, not greater than or equal toSF != OF`1101NL, GENot less than, greater than or equal toSF = OF`1110LE, NGless than or equal to, Not greater thanZF = 1 or SF != OF`1111NLE, Gnot less than or equal to, greater thanZF = 0 and SF = OF
INT                                                                 

Format                : INT imm4

Operation   : IF = 0
               push(FLAGS)
            push (PC)
              PC =  imm4 * 8

Flags Affected : none

Encoding : 
10010xxxxxxxi(3..0) 
Exception: double fault exception will be raised, if SP contains odd value

Description: Transfer control to one of 16 interrupt routines. The constant provides index into the Interrupt Vector Table (IVT). First IF is cleared; then FLAGS register is push into stack followed by PC. Then control transferred to desired interrupt service routine. 

INTO : Interrupt overflow

Format               : INTO

Operation       :  if OF = 1
           overflow exception raised
                      
Flags Affected:  none

Encoding        : 
10011xxx00000000
Exception: double fault exception will be raised, if SP contains odd value

Description: The overflow interrupt checks the OF flag in the FLAGS register and calls the overflow interrupt handler if the OF flag is set to 1. 

INTERRUPT RETURN

Format               : IRET 

Operation      : pop(PC)
      pop(FLAGS)

Flags Affected : all

Encoding      : 
10100xxxxxxxxxxx
Exception: stack alignment exception will be raised, if SP contains odd value

Description:  Returns program control from an interrupt handler to a program or procedure that was interrupted by generated interrupt

NO OPERATION (NOP)

Format            : NOP

Flags Affected: none

Encoding        : 
11110xxxxxxxxxxx
Description: No operation is performed, only PC is incremented 

HALT

Format                : HLT

Flags Affected   : none

Encoding        : 
11111xxxxxxxxxxx
Description: Causes the processor to enter its halt state and wait for an external interrupt or reset.











PAGE  


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HPC-16 Instruction Reference Manual





M. Umair Siddiqui

Change Log
DateDescriptionAuthorsBefore ReleaseInitial DocumentM.Umair Siddiqui Before ReleaseFormatting & editing Jawwad AsifSep-03, 2005First ReleaseM. Umair Siddiqui
Table of Contents
 TOC \o "1-3" \h \z \u  HYPERLINK  \l "__RefHeading___Toc125539112"HPC-16 Instruction Reference Manual   i
 HYPERLINK  \l "__RefHeading___Toc125539113"Change Log       ii
 HYPERLINK  \l "__RefHeading___Toc125539114"Table of Contents       iii
 HYPERLINK  \l "__RefHeading___Toc125539115"Instruction set reference     1
 HYPERLINK  \l "__RefHeading___Toc125539116"MOVE   1
 HYPERLINK  \l "__RefHeading___Toc125539117"MOV/COPY (register operand)     1
 HYPERLINK  \l "__RefHeading___Toc125539118"Move/Copy (to stack pointer from reg) 1
 HYPERLINK  \l "__RefHeading___Toc125539119"Move/Copy (to reg from stack pointer) 1
 HYPERLINK  \l "__RefHeading___Toc125539120"LOAD WORD 2
 HYPERLINK  \l "__RefHeading___Toc125539121"Load word from memory (register indirect mode)       2
 HYPERLINK  \l "__RefHeading___Toc125539122"Load word from memory (register indirect + imm16) 2
 HYPERLINK  \l "__RefHeading___Toc125539123"Load word from memory (using  sp )       2
 HYPERLINK  \l "__RefHeading___Toc125539124"Load word from memory ( sp  + imm16)   3
 HYPERLINK  \l "__RefHeading___Toc125539125"STORE WORD       3
 HYPERLINK  \l "__RefHeading___Toc125539126"Store word to memory (register indirect mode) 3
 HYPERLINK  \l "__RefHeading___Toc125539127"Store word to memory (register indirect + imm16)   4
 HYPERLINK  \l "__RefHeading___Toc125539128"Store word to memory (using  sp ) 4
 HYPERLINK  \l "__RefHeading___Toc125539129"Store word to memory (sp + imm16) 4
 HYPERLINK  \l "__RefHeading___Toc125539130"LOAD BYTE 5
 HYPERLINK  \l "__RefHeading___Toc125539131"Load Byte from memory with zero ext (register indirect mode): 5
 HYPERLINK  \l "__RefHeading___Toc125539132"Load Byte from memory with zero ext (register indirect + imm16):   5
 HYPERLINK  \l "__RefHeading___Toc125539133"Load byte from memory with sign ext (register indirect mode): 5
 HYPERLINK  \l "__RefHeading___Toc125539134"Load byte from memory with sign ext (register indirect + displacement mode)     6
 HYPERLINK  \l "__RefHeading___Toc125539135"STORE BYTE       6
 HYPERLINK  \l "__RefHeading___Toc125539136"Store byte to memory (register indirect mode) 6
 HYPERLINK  \l "__RefHeading___Toc125539137"Store byte to memory (register indirect + imm16)   7
 HYPERLINK  \l "__RefHeading___Toc125539138"LOAD IMMIDIATE       7
 HYPERLINK  \l "__RefHeading___Toc125539139"Load 16-bit immediate value (constant) to register from memory       7
 HYPERLINK  \l "__RefHeading___Toc125539140"Load 16-bit immediate value (constant) to  sp  from memory       7
 HYPERLINK  \l "__RefHeading___Toc125539141"INC/DEC     8
 HYPERLINK  \l "__RefHeading___Toc125539142"Increment (register operand)   8
 HYPERLINK  \l "__RefHeading___Toc125539143"Decrement (register operand)   8
 HYPERLINK  \l "__RefHeading___Toc125539144"ALU OPERATIONS       8
 HYPERLINK  \l "__RefHeading___Toc125539145"Subtract (register operands)   8
 HYPERLINK  \l "__RefHeading___Toc125539146"And (register operands)     9
 HYPERLINK  \l "__RefHeading___Toc125539147"Add (register operands)     9
 HYPERLINK  \l "__RefHeading___Toc125539148"Add with carry (register operands)       9
 HYPERLINK  \l "__RefHeading___Toc125539149"Subtract with borrow (register operands)   10
 HYPERLINK  \l "__RefHeading___Toc125539150"Logical inclusive or (register operands) 10
 HYPERLINK  \l "__RefHeading___Toc125539151"Exclusive or (register operands) 10
 HYPERLINK  \l "__RefHeading___Toc125539152"Logical not (register operand)     11
 HYPERLINK  \l "__RefHeading___Toc125539153"ALU OPERATIONS IMMIDIATE 11
 HYPERLINK  \l "__RefHeading___Toc125539154"Subtract (register and immediate operands)     11
 HYPERLINK  \l "__RefHeading___Toc125539155"logical and (register and immediate operands)       11
 HYPERLINK  \l "__RefHeading___Toc125539156"Addition (register and immediate operands)     12
 HYPERLINK  \l "__RefHeading___Toc125539157"Add with carry (register and immediate operands) 12
 HYPERLINK  \l "__RefHeading___Toc125539158"Subtract with borrow (register and immediate operands)     12
 HYPERLINK  \l "__RefHeading___Toc125539159"Logical inclusive or (register and immediate operands)     13
 HYPERLINK  \l "__RefHeading___Toc125539160"Exclusive or (register and immediate operands)     13
 HYPERLINK  \l "__RefHeading___Toc125539161"ADD/SUB-I SP 13
 HYPERLINK  \l "__RefHeading___Toc125539162"Addition (Stack pointer and immediate operands)   13
 HYPERLINK  \l "__RefHeading___Toc125539163"Subtract (Stack operation and immediate operands)       14
 HYPERLINK  \l "__RefHeading___Toc125539164"FLAG OPERATION     14
 HYPERLINK  \l "__RefHeading___Toc125539165"Compare two register operands       14
 HYPERLINK  \l "__RefHeading___Toc125539166"Logical Comparison between register operands 14
 HYPERLINK  \l "__RefHeading___Toc125539167"FLAG OPERATION IMMIDIATE 15
 HYPERLINK  \l "__RefHeading___Toc125539168"Compare (register and immediate operands)       15
 HYPERLINK  \l "__RefHeading___Toc125539169"Logical Compare (register and immediate operands)       15
 HYPERLINK  \l "__RefHeading___Toc125539170"SHIFT OPERATION   16
 HYPERLINK  \l "__RefHeading___Toc125539171"Shift logical left (register operand)       16
 HYPERLINK  \l "__RefHeading___Toc125539172"Shift logical right (register operand)     16
 HYPERLINK  \l "__RefHeading___Toc125539173"Shift arithmetic left (register operand) 16
 HYPERLINK  \l "__RefHeading___Toc125539174"Shift arithmetic right (register operand)       17
 HYPERLINK  \l "__RefHeading___Toc125539175"Rotate left (register operands)   17
 HYPERLINK  \l "__RefHeading___Toc125539176"Rotate right (register operand)   18
 HYPERLINK  \l "__RefHeading___Toc125539177"Rotate carry left (register operand) 18
 HYPERLINK  \l "__RefHeading___Toc125539178"Rotate carry right (register operand)       18
 HYPERLINK  \l "__RefHeading___Toc125539179"SHIFT IMMEDIATE   19
 HYPERLINK  \l "__RefHeading___Toc125539180"Shift logical left (imm4 operand)       19
 HYPERLINK  \l "__RefHeading___Toc125539181"Shift logical right (imm4 operand)     19
 HYPERLINK  \l "__RefHeading___Toc125539182"Shift arithmetic left (imm4 operand) 19
 HYPERLINK  \l "__RefHeading___Toc125539183"Shift arithmetic right (imm4 operand)       20
 HYPERLINK  \l "__RefHeading___Toc125539184"Rotate left (imm4 operand)     20
 HYPERLINK  \l "__RefHeading___Toc125539185"Rotate right (imm4 operand)   21
 HYPERLINK  \l "__RefHeading___Toc125539186"Rotate carry left (imm4 operand) 21
 HYPERLINK  \l "__RefHeading___Toc125539187"Rotate carry right (imm4 operand)       21
 HYPERLINK  \l "__RefHeading___Toc125539188"STACK       22
 HYPERLINK  \l "__RefHeading___Toc125539189"Push register onto the stack 22
 HYPERLINK  \l "__RefHeading___Toc125539190"Push FLAGS onto the stack       22
 HYPERLINK  \l "__RefHeading___Toc125539191"Pop word off stack to destination register     22
 HYPERLINK  \l "__RefHeading___Toc125539192"Pop word off stack to FLAGS   23
 HYPERLINK  \l "__RefHeading___Toc125539193"CALL 23
 HYPERLINK  \l "__RefHeading___Toc125539194"Procedure Call (absolute address)       23
 HYPERLINK  \l "__RefHeading___Toc125539195"Procedure Call (relative address)       24
 HYPERLINK  \l "__RefHeading___Toc125539196"Procedure Call (relative call with imm11)       24
 HYPERLINK  \l "__RefHeading___Toc125539197"RETURN     24
 HYPERLINK  \l "__RefHeading___Toc125539198"FLAG OPERATIONS   25
 HYPERLINK  \l "__RefHeading___Toc125539199"CLC : Clear Carry       25
 HYPERLINK  \l "__RefHeading___Toc125539200"STC : Set Carry Flag 25
 HYPERLINK  \l "__RefHeading___Toc125539201"CMC : Complement Carry Flag   25
 HYPERLINK  \l "__RefHeading___Toc125539202"CLI : Clear Interrupt Flag     26
 HYPERLINK  \l "__RefHeading___Toc125539203"STI : Set Interrupt flag 26
 HYPERLINK  \l "__RefHeading___Toc125539204"JMP   26
 HYPERLINK  \l "__RefHeading___Toc125539205"JMP (absolute address)     26
 HYPERLINK  \l "__RefHeading___Toc125539206"JMP (relative address)     27
 HYPERLINK  \l "__RefHeading___Toc125539207"JMP (relative call with imm11)     27
 HYPERLINK  \l "__RefHeading___Toc125539208"JCC (conditional)       27
 HYPERLINK  \l "__RefHeading___Toc125539209"INT   28
 HYPERLINK  \l "__RefHeading___Toc125539210"INTO : Interrupt overflow       28
 HYPERLINK  \l "__RefHeading___Toc125539211"INTERRUPT RETURN 29
 HYPERLINK  \l "__RefHeading___Toc125539212"NO OPERATION (NOP)     29
 HYPERLINK  \l "__RefHeading___Toc125539213"HALT 29
Instruction set reference

MOVE

MOV/COPY (register operand)

Format          : MOV rn, rm

Operation :  rn = rm

Flags Affected: none

Encoding   : 
00000001nnnnmmmm

Description: Copies the source register (rm) to destination register (rn)

Move/Copy (to stack pointer from reg)

Format          : MOV sp, mmmm

Operation     :  SP = rm

Flags Affected: none

Encoding   : 
00000010xxxxmmmm

Description: Copies the source register (rm) to stack pointer (sp)

Move/Copy (to reg from stack pointer)

Format        : MOV nnnn, s     
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Operation  :  rn = sp

Flags Affected: none

Encoding   :
00000100nnnnxxxx
Description: Copies the stack pointer (sp) to destination register (rn)


LOAD WORD

Load word from memory (register indirect mode)

Format        : LD rn, (rb)

Operation      :  rn = Memory[rb]

Flags Affected:  none

Encoding : 
00001000nnnnbbbb
Exceptions: Alignment exception will be raised in case of accessing misaligned word. 

Description: load the word data from memory at address present in "rb" register.


Load word from memory (register indirect + imm16)

Format              : LD rn, (rb + 0xhhhh)

Operation    :  rn = Memory[rb + 0xhhhh]

Flags Affected:  none

Encoding       : 
00001001nnnnbbbb imm16

Exceptions: Alignment exception will be raised in case of accessing misaligned word. 

Description: Calculate the effective address by adding the content of "rb" register and 16-bit signed constant and load the word data from memory present at effective address. 


Load word from memory (using  sp )

Format          : LD rn, (sp)

Operation      :  rn = Memory[sp]

Flags Affected:  none

Encoding : 
00001010nnnnxxxx
Description: load the word data from memory at address present in "sp" stack pointer.


Load word from memory ( sp  + imm16)

Format            : LD rn, (sp + 0xhhhh)

Operation    :  rn = Memory[sp + 0xhhhh]

Flags Affected:  none

Encoding       : 
00001100nnnnxxxx  imm16
Description: Calculate the effective address by adding the content of "sp" stack pointer and 16-bit signed constant and load the word data from memory present at effective address. 



STORE WORD

Store word to memory (register indirect mode)

Format              : ST rn, (rb)

Operation      : Memory[rb] = rn

Flags Affected: none

Encoding     : 
00010000nnnnbbbb
Exception:  Alignment exception will be raised in case of accessing misaligned word

Description: store the register content into memory at address present in "rb" register

Store word to memory (register indirect + imm16)

Format        : ST rn, (rb + imm16)

Operation      : Memory[rb + imm16] = rn

Flags Affected: none

Encoding     : 
00010001nnnnbbbb  imm16
Exceptions: Alignment exception will be raised in case of accessing misaligned word

Description: Calculate the effective address by adding the content of "rb" register and 16-bit signed constant and store the register content into memory at effective address. 

Store word to memory (using  sp )

Format          : ST rn, (sp)

Operation      : Memory[sp] = rn

Flags Affected: none

Encoding     : 
00010010nnnnxxxx
Exception:  Alignment exception will be raised in case of accessing misaligned word

Description: store the register content into memory at address present in "sp" stack pointer.

Store word to memory (sp + imm16)

Format          : ST rn, (sp + imm16)

Operation      : Memory[sp + imm16] = rn

Flags Affected: none

Encoding     : 
00010100nnnnxxxx imm16
Exceptions: Alignment exception will be raised in case of accessing misaligned word

Description: Calculate the effective address by adding the content of "sp" stack pointer and 16-bit signed constant and store the register content into memory at effective address. 


LOAD BYTE

Load Byte from memory with zero ext (register indirect mode):

Format          : LBZX rn , (rb)

Operation        : rn = zero ext( Memory[rb]) 

Flags Affected: none

Encoding     : 
00011000nnnnbbbb
Description: using the base address, load the lower byte of destination register with the content at the base address and fill the upper byte of destination register with all zeros.

Load Byte from memory with zero ext (register indirect + imm16):

Format              : LBZX rn , ( rb + imm16)

Operation      : rn = zero ext( Memory[rb + imm16]) 

Flags Affected: none

Encoding     : 
00011100nnnnbbbb imm16
Description: Calculate the effective address by adding the content in base register with a 16-bit signed constant and load the lower byte of destination register with the content at the effective address and fill the upper byte of destination register with all zeros.

Load byte from memory with sign ext (register indirect mode):                                           
Format        : LBSX rn , (rb)

Operation        :  rn = sign ext(Memory[rb])

Flags Affected:  none


Encoding   : 
00011001nnnnbbbb
Description: Using the base address load the lower byte of destination register with the content at the base address and fill the upper byte of destination register with the MSB of the lower byte.

Load byte from memory with sign ext (register indirect + displacement mode)                                             
Format        : LBSX rn , ( rb + imm16)

Operation      :  rn = sign ext(Memory[ rb+ imm16])

Flags Affected:  none

Encoding     : 
00011101nnnnbbbb imm16
Description: Calculate the effective address by adding the value of base register with a 16-bit signed immediate value and load the lower byte of destination register with the content at the effective address and fill the upper byte of destination register with the MSB of the lower byte.

STORE BYTE

Store byte to memory (register indirect mode)                                   

Format              : SB rn, (rb)

Operation      : Memory[ rb ] = rn

Flags Affected: none

Encoding :    
00100001nnnnbbbb
Description     : Using the base address, store the lower byte of destination register at the location pointed by the base address.

Store byte to memory (register indirect + imm16)
                               
Format        : SB rn, ( rb + imm16)

Operation    : Memory[ rb + imm16] = rn

Flags Affected: none

Encoding   : 
00100010nnnnbbbb imm16
Description     : Calculate the effective address by adding the value of base register with a 16-bit signed immediate value and store the lower byte of destination register at the location pointed by the effective address.


LOAD IMMIDIATE

Load 16-bit immediate value (constant) to register from memory

Format              : LI rn , imm16

Operation   :  rn = imm16

Flags Affected : none

Encoding   : 
01001001Nnnnxxxx imm16
Description: Load immediate/constant 16-bit data to the destination register

Load 16-bit immediate value (constant) to  sp  from memory

Format            : LI sp , imm16

Operation   :  sp = imm16

Flags Affected : none

Encoding   : 
01001010xxxxxxxx imm16
Description: Load immediate/constant 16-bit data to the stack pointer.



INC/DEC

Increment (register operand)

Format              : INC rn

Operation : rn = rn + 1

Flags Affected: CF is preserved while OF, SF, ZF are set according to result

Encoding    : 
00101001nnnnxxxx
Description: Add 1 to destination register while preserving the state of CF. 

Decrement (register operand) 

Format            : DEC rn

Operation :  rn = rn - 1 

Flags Affected: CF is preserved while OF, SF, ZF are set according to result

Encoding : 
00101000nnnnxxxx
Description: Subtract 1 from destination register while preserving the state of CF. 

ALU OPERATIONS

Subtract (register operands)

Format        : SUB rn, rm

Operation        : rn = rn   rm 

Flags Affected: OF, SF, ZF, CF are set according to result

Encoding     : 
00110000nnnnmmmm
Description: Subtract source register from destination register and store result in destination register

And (register operands)

Format          : AND rn, rm

Operation :  rn = rn AND rm 

Flags Affected:  OF and CF cleared, SF and ZF are set according to result 

Encoding       : 
00110101nnnnmmmm
Description: Perform bitwise AND operation between destination register and source register and store the result in destination register.

Add (register operands)

Format        : ADD rn, rm

Operation : rn = rm + rn

Flags Affected:   OF, SF, ZF and CF are affected according to result  

Encoding       : 
00110001nnnnmmmm
Description: Add destination register and source register, and store result in destination register

Add with carry (register operands)

Format              : ADC rn, rm

Operation : rn = rn + rm + CF               

Flags Affected:  OF, SF, ZF, CF are affected according to result 

Encoding :  
00110011nnnnmmmm
Description     :  Add the destination register, source register and CF, and store result in destination register. ADC instruction is useful for multi word addition

Subtract with borrow (register operands)

Format          : SBB rn, rm

Operation : rn = rn   (rm + CF)

Flags Affected :  OF, SF, ZF, CF affected according to result 

Encoding :  
00110010nnnnmmmm
Description: Add the source register with CF and subtract the result from destination register, and store result in destination register. SBB is useful for multi word subtraction.

Logical inclusive or (register operands)

Format        : OR rn, rm

Operation   :  rn = rn OR rm

Flags Affected :  OF and CF are cleared, SF and ZF are set according to result 

Encoding :  
00110110nnnnmmmm
Description: Perform bitwise OR operation between destination and source registers and store the result in destination register.  

Exclusive or (register operands)

Format          : XOR rn, rm

Operation :  rn = rn XOR rm

Flags Affected:  OF, CF are cleared, ZF and SF set according to result 

Encoding       : 
00110111nnnnmmmm
Description: Perform bitwise XOR operation between destination and source registers and store the result in destination register.


Logical not (register operand)

Format        : NOT rn

Operation :  rn = NOT (rn)

Flags Affected: none

Encoding       : 
00110100nnnnmmmm
Description: Performs bitwise-NOT operation on destination register (rn).

ALU OPERATIONS IMMIDIATE

Subtract (register and immediate operands)

Format              : SUB rn, imm16

Operation  : rn = rn   imm16 

Flags Affected:  OF, SF, ZF, CF are set to according result 

Encoding   : 
01010000nnnnxxxx imm16
Description   : Subtract immediate 16-bit data from destination register and store the result in the destination register rn .


logical and (register and immediate operands)

Format        : AND rn, imm16

Operation   : rn = rn AND imm16

Flags Affected:   OF and CF are cleared, ZF and SF are set according to result  

Encoding : 
01010101nnnnxxxx imm16
Description:     Perform bitwise AND operation between  rn  and 16-bit constant and store result in  rn .

Addition (register and immediate operands)

Format          : ADD rn, imm16

Operation   : rn  = rn + imm16

Flags Affected:  OF, SF, ZF, CF are affected according to result. 

Encoding       : 
01010001nnnnxxxx imm16

Description: Add content of rn and 16-bit constant and store rn

Add with carry (register and immediate operands)

Format        : ADC rn, imm16

Operation   :   rn = rn + imm16 + CF
     
Flags Affected:   OF, SF, ZF, CF are affected according to result 

Encoding     : 
01010011nnnnxxxx imm16
Description: Add the destination register, 16-bit constant and CF, and store result in destination register. ADC instruction is useful for multi word addition

Subtract with borrow (register and immediate operands)

Format        : SBB rn, imm16

Operation   :  rn = rn   (imm16 + CF)

Flags Affected: OF, SF, ZF, CF are set according to result 

Encoding       :  
01010010nnnnxxxx imm16
Description: Add the source register with CF and subtract the result from destination register, and store result in destination register. SBB is useful for multi word subtraction.

Logical inclusive or (register and immediate operands)

Format            : OR reg_dest, imm16

Operation : reg_dest = reg_dest OR imm16 

Flags Affected:  OF, CF are cleared and SF, ZF set according to result 

Encoding   : 
01010110nnnnxxxx imm16
Description: Performs bitwise OR operation between content of reg_dest and 16-bit constant and store result in destination register.

Exclusive or (register and immediate operands)

Format            : XOR rn, imm16

Operation   : rn = rn XOR imm16

Flags Affected:   OF, CF are cleared and ZF, SF are set according to result 

Encoding : 
01010111nnnnxxxx imm16
Description: Performs bitwise XOR operation between content of  rn  and 16-bit constant and store result in destination result 


ADD/SUB-I SP

Addition (Stack pointer and immediate operands)

Format              : ADD sp, imm16

Operation   : sp  = sp + imm16

Flags Affected:  OF, SF, ZF, CF are affected according to result. 

Encoding       :  
01101001xxxxxxxx imm16
Description: Add content of stack pointer  sp  and 16-bit constant and store  sp .

Subtract (Stack operation and immediate operands)

Format        : SUB sp, imm16

Operation  : sp = sp   imm16 

Flags Affected:  OF, SF, ZF, CF are set to according result 

Encoding   : 
01101000xxxxxxxx imm16

Description   : Subtract immediate 16-bit data from stack pointer sp  and store the result in the  sp .


FLAG OPERATION

Compare two register operands

Format            : CMP rn, rm

Operation        : temp = rn   rm
     ModifyStatusFlags;

Flags Affected: OF, SF, ZF, CF are set according 

Encoding : 
01000000nnnnmmmm
Description: compare two register operands and set the status flags. Without affecting operands the comparison is performed by subtracting  rn  from  rm  and setting the status flags in same manner as the SUB instruction. 

Logical Comparison between register operands 

Format          : TEST rn, rm

Operation       : temp = rn AND rm
        ModifyStatusFlags

Flags Affected : OF, CF are cleared, SF and ZF are set according to result 

Encoding       : 
01000101nnnnmmmm
Description: Perform logical comparison between both register operands. Without affecting operands the comparison is performed by bitwise-AND operation between  rn  and  rm  and setting the status flags in same manner as the AND instruction. 


FLAG OPERATION IMMIDIATE

Compare (register and immediate operands)  

Format        : CMP rn, imm16

Operation  : temp = rn   imm16
       ModifyStatusFlags;

Flags Affected: OF, SF, ZF, CF are set according 

Encoding : 
01100000nnnnxxxx imm16
Description: compare register operand with 16-bit constant and set the status flags. Without affecting operands the comparison is performed by subtracting the constant from rn and setting the status flags in same manner as the SUB instruction. 

Logical Compare (register and immediate operands)

Format              : TEST rn, imm16

Operation : temp = rn AND imm16
          ModifyStatusFlags

Flags Affected : OF, CF are cleared, SF and ZF are set according to result 

Encoding       : 
01100101nnnnxxxx imm16
Description: Perform logical comparison between register operand and 16-bit constant. Without affecting operands the comparison is performed by bitwise-AND operation between reg1 and constant and setting the status flags in same manner as the AND instruction. 


SHIFT OPERATION

Shift logical left (register operand)

Format          : SLL rn, rm
                                      
Operation   :  rn << rm
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
00111000 nnnnmmmm  	
Description: Shifts the bits in the destination register to the left by the number of bits specified in the  rm  register. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift logical right (register operand) 

Format		: SLR rn, rm

Operation	:  rn >>> rm

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding  : 
00111001nnnnmmmm
Description: Shifts the bits in the destination register to the right by the number of bits specified in the  rm  register. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic left (register operand) 
 
Format          : SAL rn, rm
                                      
Operation   :  rn << rm
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
00111010nnnnmmmm	
Description: Shifts the bits in the destination register to the left by the number of bits specified in the  rm  register. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic right (register operand)

Format		: SAR rn, rm

Operation	:  rn >>> rm

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding  : 
00111011nnnnmmmm
Description: Shifts the bits in the destination register to the right by the number of bits specified in the  rm  register. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit retained its original value. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Rotate left (register operands)

Format              : ROL rn , rm

Operation       : rotate_left(rn), rm times

Flags          : The CF flag contains the value of the bit shifted into it

Encoding     : 
00111100nnnnmmmm
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified in the  rm  register) toward more-significant bit positions, except for the most-significant bit, which is rotated to the least significant bit location and stores the result in the destination operand.

Rotate right (register operand)

Format            : ROR rn , rm

Operation       : rotate_right(rn), rm times

Flags Affected :  The CF flag contains the value of the bit shifted into it

Encoding : 
00111101nnnnmmmm
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified in the  rm  register) toward less-significant bit positions, except for the least-significant bit, which is rotated to the most significant bit location and stores the result in the destination operand.

Rotate carry left (register operand)

Format          : RCL rn, rm

Operation : rotate_left_with_carry(rn), rm times

Flags Affected:  The CF flag contains the value of the bit shifted into it 

Encoding     : 
00111110nnnnmmmm
Description: The Instruction rotates the  rnn to the left through CF resulting in the MSB being placed in the CF and old CF ended in the LSB. The  rm  defines the number of rotations.    

Rotate carry right (register operand)

Format        : RCR rn, rm

Operation : rotate_right_with_carry(rn), rm times

Flags Affected:   The CF flag contains the value of the bit shifted into it

Encoding   : 
00111111nnnnmmmm
Description: The Instruction rotates the  rn  to the right through CF resulting in the LSB being placed in the CF and old CF ended in the MSB. The  rm  defines the number of rotations

SHIFT IMMEDIATE

Shift logical left (imm4 operand)

Format              : SLL rn, imm(3:0)
                                  
Operation   :  rn << imm(3:0)
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
01011000nnnnimm(3..0)	
Description: Shifts the bits in the destination register to the left by the number of bits specified by the 4 bit immediate value. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift logical right (imm4 operand) 

Format		: SLR rn, imm(3:0)

Operation	:  rn >>> imm(3:0)

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding      : 
01011001nnnnimm(3..0)
Description: Shifts the bits in the destination register to the right by the number of bits specified by the 4 bit immediate value. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.
Shift arithmetic left (imm4 operand) 
 
Format          : SAL rn, imm(3:0)
                                  
Operation   :  rn << imm(3:0)
	
Flags Affected:   The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result  

Encoding	: 
01011010nnnnimm(3..0)	
Description: Shifts the bits in the destination register to the left by the number of bits specified by the 4 bit immediate value. For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

Shift arithmetic right (imm4 operand)

Format		: SAR rn, imm(3:0)

Operation	:  rn >>> imm(3:0)

Flags Affected :  The CF flag contains the value of the last bit shifted out of the destination operand; SF and ZF are set according to result     

Encoding      : 
01011011nnnnimm(3..0)
Description: Shifts the bits in the destination register to the right by the number of bits specified by the 4 bit immediate value. For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit retained its original value. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.


Rotate left (imm4 operand)

Format            : ROL rn , imm(3:0)

Operation   : rotate_left(rn), imm times

Flags        : The CF flag contains the value of the bit shifted into it



Encoding : 
01011100nnnnimm(3..0)
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified by the 4 bit immediate value) toward more-significant bit positions, except for the most-significant bit, which is rotated to the least significant bit location and stores the result in the destination operand.


Rotate right (imm4 operand)

Format        : ROR rn , imm(3:0)

Operation   : rotate_right(rn), imm times

Flags Affected :  The CF flag contains the value of the bit shifted into it

Encoding       : 
01011101Nnnnimm(3..0)
Description: Shifts (rotates) the bits of the destination register the number of bit positions (as specified by the 4 bit immediate value) toward less-significant bit positions, except for the least-significant bit, which is rotated to the most significant bit location and stores the result in the destination operand.

Rotate carry left (imm4 operand)

Format        : RCL rn, imm(3:0)

Operation     : rotate_left_with_carry(rn), imm times

Flags Affected:  The CF flag contains the value of the bit shifted into it 

Encoding   : 
01011110nnnnimm(3..0)
Description: The Instruction rotates the  rn  to the left through CF resulting in the MSB being placed in the CF and old CF ended in the LSB. The 4 bit immediate value defines the number of rotations.    

Rotate carry right (imm4 operand)

Format            : RCR rn, imm(3:0)

Operation     : rotate_right_with_carry(rn), imm times

Flags Affected:   The CF flag contains the value of the bit shifted into it

Encoding : 
01011111nnnnimm(3..0)
Description: The Instruction rotates the  rn  to the right through CF resulting in the LSB being placed in the CF and old CF ended in the MSB. The 4 bit immediate value defines the number of rotations


STACK

Push register onto the stack

Format              : PUSH rn

Operation       : SP = SP   2
   Memory[SP] = rn

Flags Affected:  none

Encoding      : 
01110000nnnnxxxx  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Decrement the stack pointer (SP) by 2 and then transfers the register content to the new top of the stack. 

Push FLAGS onto the stack

Format          : PUSHF
 
Operation : SP = SP   2 
 Memory[SP] = FLAGS

Flags Affected:  none

Encoding        :  
01110001xxxxxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Decrement the SP by 2 and then transfers FLAGS register to the new top of the stack.

Pop word off stack to destination register

Format        : POP rn

Operation :  rn = Memory[SP]
    SP = SP + 2

Flags Affected:  none

Encoding        : 
01110100nnnnxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: The content of the register `rn  is replaced by the word at the top of stack and SP is incremented by 2. 

Pop word off stack to FLAGS

Format              : POPF

Operation     : FLAGS = Memory[SP]
       SP = SP + 2

Flags Affected:  All flags are affected (including interrupt flag) 

Encoding      : 
01110101xxxxxxxx
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: Transfer the memory word into FLAGS register and increment the SP by 2.

CALL

Procedure Call (absolute address)

Format          : ACALL (rb)

Operation :  temp = rb 
      push( PC )
      PC = temp

Flags Affected:   none

Encoding   :    
01111001xxxxbbbb  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: The address of the next sequential instruction is pushed on to the stack and the control is transferred to the base address  

Procedure Call (relative address)

Format        : LCALL (rb)

Operation :  temp = rb                    
        push( PC )
      PC = PC + temp

Flags Affected:   none

Encoding :    
01111010xxxxbbbb  
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description:  PC will be added to temp and then the PC will be updated.


Procedure Call (relative call with imm11)

Format            : SCALL  imm11

Operation     :  temp = sign ext(imm11)                  
        push( PC )
      PC = PC + temp

Flags Affected:   none

Encoding :    
10000imm(10& ..0)
 
Exceptions: stack alignment exception will be raised, if SP contains odd value

Description: 11-bit immediate value with sign extension will be loaded into PC

RETURN

Format		: RET

Operation	: pop(PC)

Flags Affected : none

Encoding	: 
10001xxxxxxxxxxx
Exception: stack alignment exception will be raised, if SP contains odd value

Description: Return control after the called procedure has been executed. PC is updated by popping one word from the stack

FLAG OPERATIONS

CLC : Clear Carry

Format 	: CLC        

Operation	: CF = 0

Flags Affected : CF

Encoding	: 
11000000xxxxXxxx
Description: Clear the carry flag

STC : Set Carry Flag

Format 	: SLC

Operation	: CF = 1

Flags Affected:  CF

Encoding	:  
11000001xxxxXxxx
Description: set the carry flag

CMC : Complement Carry Flag

Format 	: SLC

Operation	: CF = NOT( CF )

Flags Affected:  CF

Encoding	: 
11000010xxxxXxxx
Description: complement the carry flag


CLI : Clear Interrupt Flag

Format 	: CLI

Operation	: IF = 0

Flags Affected:  IF

Encoding	: 
11000100xxxxXxxx
Description: Clear the interrupt flag. As a result all the maskable external interrupts become disabled.  

STI : Set Interrupt flag
Format 	: STI

Operation	: IF = 1

Flags Affected:  IF

Encoding	: 
11000101xxxxxxxx
Description: set the interrupt flag, the processor begins responding to external, maskable interrupts 

JMP

JMP (absolute address)

Format		: AJMP (rb)

Operation	:  temp = rb 
	   PC = temp

Flags Affected:   none

Encoding	:    
10101001xxxxbbbb  

Description: The control is transferred to the base address. 


JMP (relative address)

Format		: LJMP (rb)

Operation	:  temp = rb 			
	    PC = PC+temp

Flags Affected:   none

Encoding	:    
10101010xxxxbbbb  

Description:  Pc will be added to temp and then the PC will be updated.


JMP (relative call with imm11)

Format		: SJMP  imm11

Operation	:  temp = sign ext(imm11)
	   PC = PC + temp

Flags Affected:   none

Encoding	:    
10110imm(10..0)
 
Description: 11-bit immediate value with sign extension will be loaded into PC

JCC (conditional)

Format		: Jcc  imm(6..0)
Operation	:  if condition satisfied
	   	temp = sign ext (imm(6..0))
	   	PC = PC + temp

Flags Affected:   none

Encoding	:    
10111imm(6..4)tttnimm(3..0) 
Description: 7-bit immediate value with sign extension will be loaded into PC.

tttnmnemoniccondition`0000OOverflowOF = 1`0001NOno overflowOF = 0`0010B, NAEbelow, not above or equalCF = 1`0011NB, AEnot below, above or equalCF = 0`0100E, Zequal, zeroZF = 1`0101NE, NZnot equal, not zeroZF = 0`0110BE, NAbelow or equal, not aboveCF = 1 or ZF = 1`0111NBE, Anot below or equal, aboveCF = 0 and ZF = 0`1000SsignSF = 1`1001NSnot signSF = 0`1010`1011`1100L, NGEless than, not greater than or equal toSF != OF`1101NL, GENot less than, greater than or equal toSF = OF`1110LE, NGless than or equal to, Not greater thanZF = 1 or SF != OF`1111NLE, Gnot less than or equal to, greater thanZF = 0 and SF = OF
INT									

Format		: INT imm4

Operation 	: IF = 0
		push(FLAGS)
		push (PC)
		PC =  imm4 * 8

Flags Affected : none

Encoding	: 
10010xxxxxxxi(3..0) 
Exception: double fault exception will be raised, if SP contains odd value

Description: Transfer control to one of 16 interrupt routines. The constant provides index into the Interrupt Vector Table (IVT). First IF is cleared; then FLAGS register is push into stack followed by PC. Then control transferred to desired interrupt service routine. 

INTO : Interrupt overflow

Format            : INTO

Operation     :  if OF = 1
            overflow exception raised
                 
Flags Affected:  none

Encoding       : 
10011xxx00000000
Exception: double fault exception will be raised, if SP contains odd value

Description: The overflow interrupt checks the OF flag in the FLAGS register and calls the overflow interrupt handler if the OF flag is set to 1. 

INTERRUPT RETURN

Format            : IRET 

Operation   : pop(PC)
   pop(FLAGS)

Flags Affected : all

Encoding   : 
10100xxxxxxxxxxx
Exception: stack alignment exception will be raised, if SP contains odd value

Description:  Returns program control from an interrupt handler to a program or procedure that was interrupted by generated interrupt

NO OPERATION (NOP)

Format            : NOP

Flags Affected: none

Encoding        : 
11110xxxxxxxxxxx
Description: No operation is performed, only PC is incremented 

HALT

Format              : HLT

Flags Affected     : none

Encoding       : 
11111xxxxxxxxxxx
Description: Causes the processor to enter its halt state and wait for an external interrupt or reset.














 PAGE ii


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