//
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//
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// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline
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// Project : High-Speed SDRAM Controller with adaptive bank management and command pipeline
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//
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//
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// Project Nick : HSSDRC
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// Project Nick : HSSDRC
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//
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//
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// Version : 1.0-beta
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// Version : 1.0-beta
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//
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//
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// Revision : $Revision: 1.1 $
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// Revision : $Revision: 1.1 $
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//
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//
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// Date : $Date: 2008-03-06 13:54:00 $
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// Date : $Date: 2008-03-06 13:54:00 $
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//
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//
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// Workfile : tb_top.sv
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// Workfile : tb_top.sv
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//
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//
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// Description : testbench top level
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// Description : testbench top level
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//
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//
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// HSSDRC is licensed under MIT License
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// HSSDRC is licensed under MIT License
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//
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//
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// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
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// Copyright (c) 2007-2008, Denis V.Shekhalev (des00@opencores.org)
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//
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// Permission is hereby granted, free of charge, to any person obtaining a copy of
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// this software and associated documentation files (the "Software"), to deal in
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// this software and associated documentation files (the "Software"), to deal in
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// the Software without restriction, including without limitation the rights to
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// the Software without restriction, including without limitation the rights to
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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// use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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// the Software, and to permit persons to whom the Software is furnished to do so,
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// the Software, and to permit persons to whom the Software is furnished to do so,
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// subject to the following conditions:
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// subject to the following conditions:
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//
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//
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// The above copyright notice and this permission notice shall be included in all
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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// copies or substantial portions of the Software.
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//
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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// FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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// COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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//
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//
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`include "hssdrc_timescale.vh"
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`include "hssdrc_timescale.vh"
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`include "hssdrc_define.vh"
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`include "hssdrc_define.vh"
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`include "hssdrc_timing.vh"
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`include "hssdrc_timing.vh"
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`include "hssdrc_tb_sys_if.vh"
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`include "hssdrc_tb_sys_if.vh"
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module tb_top;
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module tb_top;
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parameter cPeriod = 1000.0/pClkMHz;
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parameter cPeriod = 1000.0/pClkMHz;
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parameter cHalfPeriod = cPeriod/2.0;
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parameter cHalfPeriod = cPeriod/2.0;
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wire [pDataBits-1:0] dq;
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wire [pDataBits-1:0] dq;
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wire [pDatamBits-1:0] dqm;
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wire [pDatamBits-1:0] dqm;
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wire [pSdramAddrBits-1 :0] addr;
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wire [pSdramAddrBits-1 :0] addr;
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wire [pBaBits-1 :0] ba;
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wire [pBaBits-1 :0] ba;
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wire cke ;
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wire cke ;
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wire cs_n ;
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wire cs_n ;
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wire ras_n ;
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wire ras_n ;
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wire cas_n ;
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wire cas_n ;
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wire we_n ;
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wire we_n ;
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logic sys_write;
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logic sys_write;
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logic sys_read ;
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logic sys_read ;
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logic sys_refr ;
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logic sys_refr ;
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rowa_t sys_rowa ;
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rowa_t sys_rowa ;
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cola_t sys_cola ;
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cola_t sys_cola ;
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ba_t sys_ba ;
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ba_t sys_ba ;
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burst_t sys_burst ;
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burst_t sys_burst ;
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chid_t sys_chid_i;
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chid_t sys_chid_i;
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data_t sys_wdata ;
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data_t sys_wdata ;
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datam_t sys_wdatam;
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datam_t sys_wdatam;
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logic sys_ready ;
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logic sys_ready ;
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logic sys_use_wdata ;
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logic sys_use_wdata ;
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logic sys_vld_rdata ;
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logic sys_vld_rdata ;
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chid_t sys_chid_o ;
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chid_t sys_chid_o ;
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data_t sys_rdata ;
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data_t sys_rdata ;
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bit clk_main ;
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bit clk_main ;
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bit clk;
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bit clk;
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bit nclk;
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bit nclk;
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bit reset ;
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bit reset ;
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bit sclr ;
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bit sclr ;
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hssdrc_tb_sys_if sys_if (clk, reset, sclr);
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hssdrc_tb_sys_if sys_if (clk, reset, sclr);
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assign sys_write = sys_if.write ;
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assign sys_write = sys_if.write ;
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assign sys_read = sys_if.read ;
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assign sys_read = sys_if.read ;
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assign sys_refr = sys_if.refr ;
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assign sys_refr = sys_if.refr ;
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assign sys_rowa = sys_if.rowa ;
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assign sys_rowa = sys_if.rowa ;
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assign sys_cola = sys_if.cola ;
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assign sys_cola = sys_if.cola ;
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assign sys_ba = sys_if.ba ;
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assign sys_ba = sys_if.ba ;
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assign sys_burst = sys_if.burst ;
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assign sys_burst = sys_if.burst ;
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assign sys_chid_i = sys_if.chid_i;
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assign sys_chid_i = sys_if.chid_i;
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assign sys_wdata = sys_if.wdata ;
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assign sys_wdata = sys_if.wdata ;
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assign sys_wdatam = sys_if.wdatam;
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assign sys_wdatam = sys_if.wdatam;
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assign sys_if.ready = sys_ready ;
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assign sys_if.ready = sys_ready ;
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assign sys_if.use_wdata = sys_use_wdata ;
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assign sys_if.use_wdata = sys_use_wdata ;
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assign sys_if.vld_rdata = sys_vld_rdata ;
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assign sys_if.vld_rdata = sys_vld_rdata ;
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assign sys_if.chid_o = sys_chid_o ;
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assign sys_if.chid_o = sys_chid_o ;
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assign sys_if.rdata = sys_rdata ;
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assign sys_if.rdata = sys_rdata ;
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mt48lc2m32b2 sdram_chip (
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mt48lc2m32b2 sdram_chip (
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.Dq (dq ),
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.Dq (dq ),
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.Addr (addr ),
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.Addr (addr ),
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.Ba (ba ),
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.Ba (ba ),
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.Clk (nclk ),
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.Clk (nclk ),
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.Cke (cke ),
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.Cke (cke ),
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.Cs_n (cs_n ),
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.Cs_n (cs_n ),
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.Ras_n (ras_n),
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.Ras_n (ras_n),
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.Cas_n (cas_n),
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.Cas_n (cas_n),
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.We_n (we_n ),
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.We_n (we_n ),
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.Dqm (dqm )
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.Dqm (dqm )
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);
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);
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sdram_interpretator inter (
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sdram_interpretator inter (
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.ba (ba),
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.ba (ba),
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.cs_n (cs_n ),
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.cs_n (cs_n ),
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.ras_n(ras_n),
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.ras_n(ras_n),
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.cas_n(cas_n),
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.cas_n(cas_n),
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.we_n (we_n ),
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.we_n (we_n ),
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.a10 (addr [10] )
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.a10 (addr [10] )
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);
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);
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hssdrc_top top(
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hssdrc_top top(
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.clk (clk ),
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.clk (clk ),
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.reset (reset),
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.reset (reset),
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.sclr (sclr ),
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.sclr (sclr ),
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//
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//
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.sys_write (sys_write ),
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.sys_write (sys_write ),
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.sys_read (sys_read ),
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.sys_read (sys_read ),
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.sys_refr (sys_refr ),
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.sys_refr (sys_refr ),
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.sys_rowa (sys_rowa ),
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.sys_rowa (sys_rowa ),
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.sys_cola (sys_cola ),
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.sys_cola (sys_cola ),
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.sys_ba (sys_ba ),
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.sys_ba (sys_ba ),
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.sys_burst (sys_burst ),
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.sys_burst (sys_burst ),
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.sys_chid_i (sys_chid_i ),
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.sys_chid_i (sys_chid_i ),
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.sys_wdata (sys_wdata ),
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.sys_wdata (sys_wdata ),
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.sys_wdatam (sys_wdatam ),
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.sys_wdatam (sys_wdatam ),
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.sys_ready (sys_ready ),
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.sys_ready (sys_ready ),
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.sys_use_wdata (sys_use_wdata),
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.sys_use_wdata (sys_use_wdata),
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.sys_vld_rdata (sys_vld_rdata),
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.sys_vld_rdata (sys_vld_rdata),
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.sys_chid_o (sys_chid_o ),
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.sys_chid_o (sys_chid_o ),
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.sys_rdata (sys_rdata ),
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.sys_rdata (sys_rdata ),
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//
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//
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.dq (dq ),
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.dq (dq ),
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.dqm (dqm ),
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.dqm (dqm ),
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.addr (addr ),
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.addr (addr ),
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.ba (ba ),
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.ba (ba ),
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.cke (cke ),
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.cke (cke ),
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.cs_n (cs_n ),
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.cs_n (cs_n ),
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.ras_n (ras_n),
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.ras_n (ras_n),
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.cas_n (cas_n),
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.cas_n (cas_n),
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.we_n (we_n )
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.we_n (we_n )
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);
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);
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initial begin : clock_generator
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initial begin : clock_generator
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clk_main = 1'b0;
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clk_main = 1'b0;
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#(cHalfPeriod);
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#(cHalfPeriod);
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forever clk_main = #(cHalfPeriod) ~clk_main;
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forever clk_main = #(cHalfPeriod) ~clk_main;
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end
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end
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always_comb begin
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always_comb begin
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clk <= clk_main;
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clk <= clk_main;
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nclk <= #2 ~clk_main; // model output buffer delay
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nclk <= #2 ~clk_main; // model output buffer delay
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end
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end
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assign sclr = 1'b0;
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assign sclr = 1'b0;
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initial begin : reset_generator
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initial begin : reset_generator
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reset = 1'b1;
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reset = 1'b1;
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repeat (4) @(posedge clk);
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repeat (4) @(posedge clk);
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@(negedge clk);
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@(negedge clk);
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reset = 1'b0;
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reset = 1'b0;
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end
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end
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tb_prog prog (sys_if.tb);
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tb_prog prog (sys_if.tb);
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endmodule
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endmodule
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