----==============================================================----
|
----==============================================================----
|
---- ----
|
---- ----
|
---- Filename: mux2_1.vhd ----
|
---- Filename: mux2_1.vhd ----
|
---- Module description: 2-to-1 DW-bit multiplexer ----
|
---- Module description: 2-to-1 DW-bit multiplexer ----
|
---- ----
|
---- ----
|
---- Author: Nikolaos Kavvadias ----
|
---- Author: Nikolaos Kavvadias ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- ----
|
---- ----
|
---- ----
|
---- ----
|
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
|
---- Downloaded from: http://wwww.opencores.org/cores/hwlu ----
|
---- ----
|
---- ----
|
---- To Do: ----
|
---- To Do: ----
|
---- Probably remains as current ----
|
---- Probably remains as current ----
|
---- (to promote as stable version) ----
|
---- (to promote as stable version) ----
|
---- ----
|
---- ----
|
---- Author: Nikolaos Kavvadias ----
|
---- Author: Nikolaos Kavvadias ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- ----
|
---- ----
|
----==============================================================----
|
----==============================================================----
|
---- ----
|
---- ----
|
---- Copyright (C) 2004 Nikolaos Kavvadias ----
|
---- Copyright (C) 2004 Nikolaos Kavvadias ----
|
---- nick-kavi.8m.com ----
|
---- nick-kavi.8m.com ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- nkavv@skiathos.physics.auth.gr ----
|
---- nick_ka_vi@hotmail.com ----
|
---- nick_ka_vi@hotmail.com ----
|
---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
|
---- restriction provided that this copyright statement is not ----
|
---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- the original copyright notice and the associated disclaimer. ----
|
---- ----
|
---- ----
|
---- This source file is free software; you can redistribute it ----
|
---- This source file is free software; you can redistribute it ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- Public License as published by the Free Software Foundation; ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- either version 2.1 of the License, or (at your option) any ----
|
---- later version. ----
|
---- later version. ----
|
---- ----
|
---- ----
|
---- This source is distributed in the hope that it will be ----
|
---- This source is distributed in the hope that it will be ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
---- details. ----
|
---- details. ----
|
---- ----
|
---- ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- You should have received a copy of the GNU Lesser General ----
|
---- Public License along with this source; if not, download it ----
|
---- Public License along with this source; if not, download it ----
|
---- from <http://www.opencores.org/lgpl.shtml> ----
|
---- from <http://www.opencores.org/lgpl.shtml> ----
|
---- ----
|
---- ----
|
----==============================================================----
|
----==============================================================----
|
--
|
--
|
-- CVS Revision History
|
-- CVS Revision History
|
--
|
--
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
|
|
entity mux2_1 is
|
entity mux2_1 is
|
generic (
|
generic (
|
DW : integer := 8
|
DW : integer := 8
|
);
|
);
|
port (
|
port (
|
in0 : in std_logic_vector(DW-1 downto 0);
|
in0 : in std_logic_vector(DW-1 downto 0);
|
in1 : in std_logic_vector(DW-1 downto 0);
|
in1 : in std_logic_vector(DW-1 downto 0);
|
sel : in std_logic;
|
sel : in std_logic;
|
mout : out std_logic_vector(DW-1 downto 0)
|
mout : out std_logic_vector(DW-1 downto 0)
|
);
|
);
|
end mux2_1;
|
end mux2_1;
|
|
|
|
|
architecture rtl of mux2_1 is
|
architecture rtl of mux2_1 is
|
begin
|
begin
|
process (sel, in0, in1)
|
process (sel, in0, in1)
|
begin
|
begin
|
case sel is
|
case sel is
|
when '0' => mout <= in0;
|
when '0' => mout <= in0;
|
when others => mout <= in1;
|
when others => mout <= in1;
|
end case;
|
end case;
|
end process;
|
end process;
|
--
|
--
|
end rtl;
|
end rtl;
|
|
|
