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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_master_bit_ctrl.v,v 1.2 2001-11-05 11:59:25 rherveille Exp $
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//
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// $Date: 2001-11-05 11:59:25 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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//
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// WISHBONE revB2 compiant I2C master core, bit controller
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// Change History:
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//
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// $Log: not supported by cvs2svn $
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// author: Richard Herveille
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// rev. 0.1 August 19th, 2001. Initial Verilog release.
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//
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//
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//
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/////////////////////////////////////
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/////////////////////////////////////
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// Bit controller section
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// Bit controller section
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/////////////////////////////////////
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/////////////////////////////////////
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//
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//
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// Translate simple commands into SCL/SDA transitions
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// Translate simple commands into SCL/SDA transitions
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// Each command has 5 states, A/B/C/D/idle
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// Each command has 5 states, A/B/C/D/idle
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//
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//
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// start: SCL ~~~~~~~~~~\____
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// start: SCL ~~~~~~~~~~\____
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// SDA ~~~~~~~~\______
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// SDA ~~~~~~~~\______
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// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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// repstart SCL ____/~~~~\___
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// repstart SCL ____/~~~~\___
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// SDA __/~~~\______
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// SDA __/~~~\______
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// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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// stop SCL ____/~~~~~~~~
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// stop SCL ____/~~~~~~~~
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// SDA ==\____/~~~~~
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// SDA ==\____/~~~~~
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// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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//- write SCL ____/~~~~\____
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//- write SCL ____/~~~~\____
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// SDA ==X=========X=
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// SDA ==X=========X=
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// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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//- read SCL ____/~~~~\____
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//- read SCL ____/~~~~\____
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// SDA XXXX=====XXXX
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// SDA XXXX=====XXXX
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// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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// Timing: Normal mode Fast mode
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// Timing: Normal mode Fast mode
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///////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////
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// Fscl 100KHz 400KHz
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// Fscl 100KHz 400KHz
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// Th_scl 4.0us 0.6us High period of SCL
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// Th_scl 4.0us 0.6us High period of SCL
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// Tl_scl 4.7us 1.3us Low period of SCL
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// Tl_scl 4.7us 1.3us Low period of SCL
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// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_bit_ctrl(clk, rst, nReset, clk_cnt, ena, cmd, cmd_ack, busy, din, dout, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen);
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module i2c_master_bit_ctrl(clk, rst, nReset, clk_cnt, ena, cmd, cmd_ack, busy, din, dout, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen);
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input nReset;
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input nReset;
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input ena; // core enable signal
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input ena; // core enable signal
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input [15:0] clk_cnt; // clock prescale value
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input [15:0] clk_cnt; // clock prescale value
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input [3:0] cmd;
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input [3:0] cmd;
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output cmd_ack;
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output cmd_ack;
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reg cmd_ack;
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reg cmd_ack;
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output busy;
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output busy;
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reg busy;
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reg busy;
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input din;
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input din;
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output dout;
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output dout;
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reg dout;
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reg dout;
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// I2C lines
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// I2C lines
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input scl_i; // i2c clock line input
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input scl_i; // i2c clock line input
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output scl_o; // i2c clock line output
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output scl_o; // i2c clock line output
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output scl_oen; // i2c clock line output enable (active low)
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output scl_oen; // i2c clock line output enable (active low)
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reg scl_oen;
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reg scl_oen;
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input sda_i; // i2c data line input
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input sda_i; // i2c data line input
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output sda_o; // i2c data line output
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output sda_o; // i2c data line output
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output sda_oen; // i2c data line output enable (active low)
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output sda_oen; // i2c data line output enable (active low)
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reg sda_oen;
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reg sda_oen;
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg sSCL, sSDA; // synchronized SCL and SDA inputs
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
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wire slave_wait;
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wire slave_wait;
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
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reg [15:0] cnt; // clock divider counter (synthesis)
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reg [15:0] cnt; // clock divider counter (synthesis)
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//
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//
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// module body
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// module body
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//
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//
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// synchronize SCL and SDA inputs
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// synchronize SCL and SDA inputs
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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sSCL <= #1 scl_i;
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sSCL <= #1 scl_i;
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sSDA <= #1 sda_i;
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sSDA <= #1 sda_i;
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end
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end
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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// whenever the slave is not ready it can delay the cycle by pulling SCL low
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assign slave_wait = scl_oen && !sSCL;
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assign slave_wait = scl_oen && !sSCL;
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// generate clk enable signal
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// generate clk enable signal
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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begin
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begin
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cnt <= #1 15'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if (rst)
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else if (rst)
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begin
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begin
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cnt <= #1 15'h0;
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cnt <= #1 16'h0;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else if ( !(|cnt) || !ena)
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else if ( !(|cnt) || !ena)
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begin
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begin
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cnt <= #1 clk_cnt;
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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clk_en <= #1 1'b1;
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end
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end
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else
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else
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begin
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begin
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if (!slave_wait)
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if (!slave_wait)
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cnt <= #1 cnt - 1'h1;
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cnt <= #1 cnt - 16'h1;
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clk_en <= #1 1'b0;
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clk_en <= #1 1'b0;
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end
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end
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// generate bus status controller
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// generate bus status controller
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reg dSDA;
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reg dSDA;
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reg sta_condition;
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reg sta_condition;
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reg sto_condition;
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reg sto_condition;
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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dSDA <= #1 sSDA; // generate a delayed versio nof sSDA
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dSDA <= #1 sSDA; // generate a delayed versio nof sSDA
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sta_condition <= #1 !sSDA && dSDA && sSCL;
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sta_condition <= #1 !sSDA && dSDA && sSCL;
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sto_condition <= #1 sSDA && !dSDA && sSCL;
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sto_condition <= #1 sSDA && !dSDA && sSCL;
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end
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end
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// generate bus busy signal
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// generate bus busy signal
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
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if (!nReset)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else if (rst)
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else if (rst)
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busy <= #1 1'b0;
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busy <= #1 1'b0;
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else
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else
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busy <= (sta_condition || busy) && !sto_condition;
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busy <= (sta_condition || busy) && !sto_condition;
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// generate statemachine
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// generate statemachine
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// nxt_state decoder
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// nxt_state decoder
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parameter [14:0] idle = 15'b000_0000_0000_0000;
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parameter [14:0] idle = 15'b000_0000_0000_0000;
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parameter [14:0] start_a = 15'b000_0000_0000_0001;
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parameter [14:0] start_a = 15'b000_0000_0000_0001;
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parameter [14:0] start_b = 15'b000_0000_0000_0010;
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parameter [14:0] start_b = 15'b000_0000_0000_0010;
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parameter [14:0] start_c = 15'b000_0000_0000_0100;
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parameter [14:0] start_c = 15'b000_0000_0000_0100;
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parameter [14:0] start_d = 15'b000_0000_0000_1000;
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parameter [14:0] start_d = 15'b000_0000_0000_1000;
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parameter [14:0] stop_a = 15'b000_0000_0001_0000;
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parameter [14:0] stop_a = 15'b000_0000_0001_0000;
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parameter [14:0] stop_b = 15'b000_0000_0010_0000;
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parameter [14:0] stop_b = 15'b000_0000_0010_0000;
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parameter [14:0] stop_c = 15'b000_0000_0100_0000;
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parameter [14:0] stop_c = 15'b000_0000_0100_0000;
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parameter [14:0] rd_a = 15'b000_0000_1000_0000;
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parameter [14:0] rd_a = 15'b000_0000_1000_0000;
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parameter [14:0] rd_b = 15'b000_0001_0000_0000;
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parameter [14:0] rd_b = 15'b000_0001_0000_0000;
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parameter [14:0] rd_c = 15'b000_0010_0000_0000;
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parameter [14:0] rd_c = 15'b000_0010_0000_0000;
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parameter [14:0] rd_d = 15'b000_0100_0000_0000;
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parameter [14:0] rd_d = 15'b000_0100_0000_0000;
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parameter [14:0] wr_a = 15'b000_1000_0000_0000;
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parameter [14:0] wr_a = 15'b000_1000_0000_0000;
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parameter [14:0] wr_b = 15'b001_0000_0000_0000;
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parameter [14:0] wr_b = 15'b001_0000_0000_0000;
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parameter [14:0] wr_c = 15'b010_0000_0000_0000;
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parameter [14:0] wr_c = 15'b010_0000_0000_0000;
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parameter [14:0] wr_d = 15'b100_0000_0000_0000;
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parameter [14:0] wr_d = 15'b100_0000_0000_0000;
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reg [14:0] c_state, nxt_state; // synopsis enum_state
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reg [14:0] c_state, nxt_state; // synopsis enum_state
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reg icmd_ack, store_sda;
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reg icmd_ack, store_sda;
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always@(c_state or cmd)
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always@(c_state or cmd)
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begin
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begin
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nxt_state = c_state;
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nxt_state = c_state;
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icmd_ack = 1'b0; // default no command acknowledge
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icmd_ack = 1'b0; // default no command acknowledge
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store_sda = 1'b0;
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store_sda = 1'b0;
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case (c_state) // synopsis full_case parallel_case
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case (c_state) // synopsis full_case parallel_case
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// idle state
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// idle state
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idle:
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idle:
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case (cmd) // synopsis full_case parallel_case
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case (cmd) // synopsis full_case parallel_case
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`I2C_CMD_START:
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`I2C_CMD_START:
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nxt_state = start_a;
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nxt_state = start_a;
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`I2C_CMD_STOP:
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`I2C_CMD_STOP:
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nxt_state = stop_a;
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nxt_state = stop_a;
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`I2C_CMD_WRITE:
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`I2C_CMD_WRITE:
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nxt_state = wr_a;
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nxt_state = wr_a;
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`I2C_CMD_READ:
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`I2C_CMD_READ:
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nxt_state = rd_a;
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nxt_state = rd_a;
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default:
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default:
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nxt_state = idle;
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nxt_state = idle;
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endcase
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endcase
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// start
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// start
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start_a:
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start_a:
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nxt_state = start_b;
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nxt_state = start_b;
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start_b:
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start_b:
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nxt_state = start_c;
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nxt_state = start_c;
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start_c:
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start_c:
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nxt_state = start_d;
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nxt_state = start_d;
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start_d:
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start_d:
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begin
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begin
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nxt_state = idle;
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nxt_state = idle;
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icmd_ack = 1'b1;
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icmd_ack = 1'b1;
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end
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end
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// stop
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// stop
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stop_a:
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stop_a:
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nxt_state = stop_b;
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nxt_state = stop_b;
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stop_b:
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stop_b:
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nxt_state = stop_c;
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nxt_state = stop_c;
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stop_c:
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stop_c:
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begin
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begin
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nxt_state = idle;
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nxt_state = idle;
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icmd_ack = 1'b1;
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icmd_ack = 1'b1;
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end
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end
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// read
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// read
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rd_a:
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rd_a:
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nxt_state = rd_b;
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nxt_state = rd_b;
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rd_b:
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rd_b:
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nxt_state = rd_c;
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nxt_state = rd_c;
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rd_c:
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rd_c:
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begin
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begin
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nxt_state = rd_d;
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nxt_state = rd_d;
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store_sda = 1'b1;
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store_sda = 1'b1;
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end
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end
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rd_d:
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rd_d:
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begin
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begin
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nxt_state = idle;
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nxt_state = idle;
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icmd_ack = 1'b1;
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icmd_ack = 1'b1;
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end
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end
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// write
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// write
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wr_a:
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wr_a:
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nxt_state = wr_b;
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nxt_state = wr_b;
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wr_b:
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wr_b:
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nxt_state = wr_c;
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nxt_state = wr_c;
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|
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wr_c:
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wr_c:
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nxt_state = wr_d;
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nxt_state = wr_d;
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wr_d:
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wr_d:
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begin
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begin
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nxt_state = idle;
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nxt_state = idle;
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icmd_ack = 1'b1;
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icmd_ack = 1'b1;
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end
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end
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endcase
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endcase
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end
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end
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|
// generate registers
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// generate registers
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always@(posedge clk or negedge nReset)
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always@(posedge clk or negedge nReset)
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if (!nReset)
|
if (!nReset)
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begin
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begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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dout <= #1 1'b0;
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end
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end
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else if (rst)
|
else if (rst)
|
begin
|
begin
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c_state <= #1 idle;
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c_state <= #1 idle;
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cmd_ack <= #1 1'b0;
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cmd_ack <= #1 1'b0;
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dout <= #1 1'b0;
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dout <= #1 1'b0;
|
end
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end
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else
|
else
|
begin
|
begin
|
if (clk_en)
|
if (clk_en)
|
begin
|
begin
|
c_state <= #1 nxt_state;
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c_state <= #1 nxt_state;
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if(store_sda)
|
if(store_sda)
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dout <= #1 sSDA;
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dout <= #1 sSDA;
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end
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end
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|
|
cmd_ack <= #1 icmd_ack && clk_en;
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cmd_ack <= #1 icmd_ack && clk_en;
|
end
|
end
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|
|
//
|
//
|
// convert states to SCL and SDA signals
|
// convert states to SCL and SDA signals
|
//
|
//
|
|
|
// assign scl and sda output (always gnd)
|
// assign scl and sda output (always gnd)
|
assign scl_o = 1'b0;
|
assign scl_o = 1'b0;
|
assign sda_o = 1'b0;
|
assign sda_o = 1'b0;
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|
|
// assign scl and sda output_enables
|
// assign scl and sda output_enables
|
always@(posedge clk or negedge nReset)
|
always@(posedge clk or negedge nReset)
|
if (!nReset)
|
if (!nReset)
|
begin
|
begin
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scl_oen <= #1 1'b1;
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scl_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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end
|
else if (rst)
|
else if (rst)
|
begin
|
begin
|
scl_oen <= #1 1'b1;
|
scl_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
end
|
end
|
else if (clk_en)
|
else if (clk_en)
|
case (c_state) // synopsis full_case parallel_case
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case (c_state) // synopsis full_case parallel_case
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// idle state
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// idle state
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idle:
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idle:
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begin
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begin
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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sda_oen <= #1 sda_oen; // keep SDA in same state
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end
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end
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// start
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// start
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start_a:
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start_a:
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begin
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begin
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scl_oen <= #1 scl_oen; // keep SCL in same state
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scl_oen <= #1 scl_oen; // keep SCL in same state
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sda_oen <= #1 1'b1; // set SDA high
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sda_oen <= #1 1'b1; // set SDA high
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end
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end
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start_b:
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start_b:
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begin
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begin
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b1; // keep SDA high
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sda_oen <= #1 1'b1; // keep SDA high
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end
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end
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start_c:
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start_c:
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begin
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begin
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b0; // set SDA low
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sda_oen <= #1 1'b0; // set SDA low
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end
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end
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start_d:
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start_d:
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begin
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begin
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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// stop
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// stop
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stop_a:
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stop_a:
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begin
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begin
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 1'b0; // set SDA low
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sda_oen <= #1 1'b0; // set SDA low
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end
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end
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stop_b:
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stop_b:
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begin
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begin
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b0; // keep SDA low
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sda_oen <= #1 1'b0; // keep SDA low
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end
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end
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stop_c:
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stop_c:
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begin
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begin
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b1; // set SDA high
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sda_oen <= #1 1'b1; // set SDA high
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end
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end
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//write
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//write
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wr_a:
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wr_a:
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begin
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begin
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 din; // set SDA
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sda_oen <= #1 din; // set SDA
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end
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end
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wr_b:
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wr_b:
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begin
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begin
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 din; // keep SDA
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sda_oen <= #1 din; // keep SDA
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end
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end
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wr_c:
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wr_c:
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begin
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begin
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 din;
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sda_oen <= #1 din;
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end
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end
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wr_d:
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wr_d:
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begin
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begin
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 din;
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sda_oen <= #1 din;
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end
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end
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// read
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// read
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rd_a:
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rd_a:
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begin
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begin
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scl_oen <= #1 1'b0; // keep SCL low
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scl_oen <= #1 1'b0; // keep SCL low
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sda_oen <= #1 1'b1; // tri-state SDA
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sda_oen <= #1 1'b1; // tri-state SDA
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end
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end
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rd_b:
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rd_b:
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begin
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begin
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scl_oen <= #1 1'b1; // set SCL high
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scl_oen <= #1 1'b1; // set SCL high
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sda_oen <= #1 1'b1; // keep SDA tri-stated
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sda_oen <= #1 1'b1; // keep SDA tri-stated
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end
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end
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rd_c:
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rd_c:
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begin
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begin
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scl_oen <= #1 1'b1; // keep SCL high
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scl_oen <= #1 1'b1; // keep SCL high
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sda_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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end
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rd_d:
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rd_d:
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begin
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begin
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scl_oen <= #1 1'b0; // set SCL low
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scl_oen <= #1 1'b0; // set SCL low
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sda_oen <= #1 1'b1;
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sda_oen <= #1 1'b1;
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end
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end
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endcase
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endcase
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endmodule
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endmodule
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