/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
|
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author: Richard Herveille ////
|
//// Author: Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// www.asics.ws ////
|
//// www.asics.ws ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: i2c_master_bit_ctrl.v,v 1.4 2002-10-30 18:10:07 rherveille Exp $
|
// $Id: i2c_master_bit_ctrl.v,v 1.5 2002-11-30 22:24:40 rherveille Exp $
|
//
|
//
|
// $Date: 2002-10-30 18:10:07 $
|
// $Date: 2002-11-30 22:24:40 $
|
// $Revision: 1.4 $
|
// $Revision: 1.5 $
|
// $Author: rherveille $
|
// $Author: rherveille $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/10/30 18:10:07 rherveille
|
|
// Fixed some reported minor start/stop generation timing issuess.
|
|
//
|
// Revision 1.3 2002/06/15 07:37:03 rherveille
|
// Revision 1.3 2002/06/15 07:37:03 rherveille
|
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
//
|
//
|
// Revision 1.2 2001/11/05 11:59:25 rherveille
|
// Revision 1.2 2001/11/05 11:59:25 rherveille
|
// Fixed wb_ack_o generation bug.
|
// Fixed wb_ack_o generation bug.
|
// Fixed bug in the byte_controller statemachine.
|
// Fixed bug in the byte_controller statemachine.
|
// Added headers.
|
// Added headers.
|
//
|
//
|
|
|
//
|
//
|
/////////////////////////////////////
|
/////////////////////////////////////
|
// Bit controller section
|
// Bit controller section
|
/////////////////////////////////////
|
/////////////////////////////////////
|
//
|
//
|
// Translate simple commands into SCL/SDA transitions
|
// Translate simple commands into SCL/SDA transitions
|
// Each command has 5 states, A/B/C/D/idle
|
// Each command has 5 states, A/B/C/D/idle
|
//
|
//
|
// start: SCL ~~~~~~~~~~\____
|
// start: SCL ~~~~~~~~~~\____
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// SDA ~~~~~~~~\______
|
// SDA ~~~~~~~~\______
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
// repstart SCL ____/~~~~\___
|
// repstart SCL ____/~~~~\___
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// SDA __/~~~\______
|
// SDA __/~~~\______
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
// stop SCL ____/~~~~~~~~
|
// stop SCL ____/~~~~~~~~
|
// SDA ==\____/~~~~~
|
// SDA ==\____/~~~~~
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
//- write SCL ____/~~~~\____
|
//- write SCL ____/~~~~\____
|
// SDA ==X=========X=
|
// SDA ==X=========X=
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
//- read SCL ____/~~~~\____
|
//- read SCL ____/~~~~\____
|
// SDA XXXX=====XXXX
|
// SDA XXXX=====XXXX
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
|
|
// Timing: Normal mode Fast mode
|
// Timing: Normal mode Fast mode
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
// Fscl 100KHz 400KHz
|
// Fscl 100KHz 400KHz
|
// Th_scl 4.0us 0.6us High period of SCL
|
// Th_scl 4.0us 0.6us High period of SCL
|
// Tl_scl 4.7us 1.3us Low period of SCL
|
// Tl_scl 4.7us 1.3us Low period of SCL
|
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
|
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
|
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
//
|
//
|
|
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "i2c_master_defines.v"
|
`include "i2c_master_defines.v"
|
|
|
module i2c_master_bit_ctrl(clk, rst, nReset, clk_cnt, ena, cmd, cmd_ack, busy, din, dout, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen);
|
module i2c_master_bit_ctrl(clk, rst, nReset, clk_cnt, ena, cmd, cmd_ack, busy, din, dout, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen);
|
|
|
//
|
//
|
// inputs & outputs
|
// inputs & outputs
|
//
|
//
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input nReset;
|
input nReset;
|
input ena; // core enable signal
|
input ena; // core enable signal
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|
|
input [15:0] clk_cnt; // clock prescale value
|
input [15:0] clk_cnt; // clock prescale value
|
|
|
input [3:0] cmd;
|
input [3:0] cmd;
|
output cmd_ack;
|
output cmd_ack;
|
reg cmd_ack;
|
reg cmd_ack;
|
output busy;
|
output busy;
|
reg busy;
|
reg busy;
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|
|
input din;
|
input din;
|
output dout;
|
output dout;
|
reg dout;
|
reg dout;
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|
|
// I2C lines
|
// I2C lines
|
input scl_i; // i2c clock line input
|
input scl_i; // i2c clock line input
|
output scl_o; // i2c clock line output
|
output scl_o; // i2c clock line output
|
output scl_oen; // i2c clock line output enable (active low)
|
output scl_oen; // i2c clock line output enable (active low)
|
reg scl_oen;
|
reg scl_oen;
|
input sda_i; // i2c data line input
|
input sda_i; // i2c data line input
|
output sda_o; // i2c data line output
|
output sda_o; // i2c data line output
|
output sda_oen; // i2c data line output enable (active low)
|
output sda_oen; // i2c data line output enable (active low)
|
reg sda_oen;
|
reg sda_oen;
|
|
|
|
|
//
|
//
|
// variable declarations
|
// variable declarations
|
//
|
//
|
|
|
reg sSCL, sSDA; // synchronized SCL and SDA inputs
|
reg sSCL, sSDA; // synchronized SCL and SDA inputs
|
reg dscl_oen; // delayed scl_oen
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reg dscl_oen; // delayed scl_oen
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reg clk_en; // clock generation signals
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reg clk_en; // clock generation signals
|
wire slave_wait;
|
wire slave_wait;
|
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
|
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
|
reg [15:0] cnt; // clock divider counter (synthesis)
|
reg [15:0] cnt; // clock divider counter (synthesis)
|
|
|
//
|
//
|
// module body
|
// module body
|
//
|
//
|
|
|
// synchronize SCL and SDA inputs
|
// synchronize SCL and SDA inputs
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
sSCL <= #1 scl_i;
|
sSCL <= #1 scl_i;
|
sSDA <= #1 sda_i;
|
sSDA <= #1 sda_i;
|
end
|
end
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|
|
// delay scl_oen
|
// delay scl_oen
|
always @(posedge clk)
|
always @(posedge clk)
|
dscl_oen <= #1 scl_oen;
|
dscl_oen <= #1 scl_oen;
|
|
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
assign slave_wait = dscl_oen && !sSCL;
|
assign slave_wait = dscl_oen && !sSCL;
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|
|
// generate clk enable signal
|
// generate clk enable signal
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if(~nReset)
|
if(~nReset)
|
begin
|
begin
|
cnt <= #1 16'h0;
|
cnt <= #1 16'h0;
|
clk_en <= #1 1'b1;
|
clk_en <= #1 1'b1;
|
end
|
end
|
else if (rst)
|
else if (rst)
|
begin
|
begin
|
cnt <= #1 16'h0;
|
cnt <= #1 16'h0;
|
clk_en <= #1 1'b1;
|
clk_en <= #1 1'b1;
|
end
|
end
|
else if ( !(|cnt) || !ena)
|
else if ( !(|cnt) || !ena)
|
begin
|
begin
|
cnt <= #1 clk_cnt;
|
cnt <= #1 clk_cnt;
|
clk_en <= #1 1'b1;
|
clk_en <= #1 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(!slave_wait)
|
if(!slave_wait)
|
cnt <= #1 cnt - 16'h1;
|
cnt <= #1 cnt - 16'h1;
|
|
|
clk_en <= #1 1'b0;
|
clk_en <= #1 1'b0;
|
end
|
end
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|
|
|
|
// generate bus status controller
|
// generate bus status controller
|
reg dSDA;
|
reg dSDA;
|
reg sta_condition;
|
reg sta_condition;
|
reg sto_condition;
|
reg sto_condition;
|
|
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
dSDA <= #1 sSDA; // generate a delayed version of sSDA
|
dSDA <= #1 sSDA; // generate a delayed version of sSDA
|
|
|
sta_condition <= #1 !sSDA && dSDA && sSCL;
|
sta_condition <= #1 ~sSDA & dSDA & sSCL;
|
sto_condition <= #1 sSDA && !dSDA && sSCL;
|
sto_condition <= #1 sSDA & ~dSDA & sSCL;
|
end
|
end
|
|
|
// generate bus busy signal
|
// generate bus busy signal
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if(!nReset)
|
if(!nReset)
|
busy <= #1 1'b0;
|
busy <= #1 1'b0;
|
else if (rst)
|
else if (rst)
|
busy <= #1 1'b0;
|
busy <= #1 1'b0;
|
else
|
else
|
busy <= #1 (sta_condition || busy) && !sto_condition;
|
busy <= #1 (sta_condition | busy) & ~sto_condition;
|
|
|
|
|
// generate statemachine
|
// generate statemachine
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|
|
// nxt_state decoder
|
// nxt_state decoder
|
parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
|
parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
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parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
|
parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
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parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
|
parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
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parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
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parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
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parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
|
parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
|
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
|
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
|
parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
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parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
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parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
|
parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
|
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
|
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
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parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
|
parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
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parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
|
parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
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parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
|
parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
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parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
|
parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
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parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
|
parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
|
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
|
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
|
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
|
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
|
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
|
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
|
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
|
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
|
|
|
reg [16:0] c_state, nxt_state; // synopsis enum_state
|
reg [16:0] c_state; // synopsis enum_state
|
reg icmd_ack, store_sda;
|
|
|
|
always @(c_state or cmd)
|
|
begin
|
|
nxt_state = c_state;
|
|
icmd_ack = 1'b0; // default no command acknowledge
|
|
store_sda = 1'b0;
|
|
|
|
case (c_state) // synopsis full_case parallel_case
|
|
// idle state
|
|
idle:
|
|
case (cmd) // synopsis full_case parallel_case
|
|
`I2C_CMD_START:
|
|
nxt_state = start_a;
|
|
|
|
`I2C_CMD_STOP:
|
|
nxt_state = stop_a;
|
|
|
|
`I2C_CMD_WRITE:
|
|
nxt_state = wr_a;
|
|
|
|
`I2C_CMD_READ:
|
|
nxt_state = rd_a;
|
|
|
|
default:
|
|
nxt_state = idle;
|
|
|
|
endcase
|
|
|
|
// start
|
|
start_a:
|
|
nxt_state = start_b;
|
|
|
|
start_b:
|
|
nxt_state = start_c;
|
|
|
|
start_c:
|
|
nxt_state = start_d;
|
|
|
|
start_d:
|
|
nxt_state = start_e;
|
|
|
|
start_e:
|
|
begin
|
|
nxt_state = idle;
|
|
icmd_ack = 1'b1;
|
|
end
|
|
|
|
// stop
|
|
stop_a:
|
|
nxt_state = stop_b;
|
|
|
|
stop_b:
|
|
nxt_state = stop_c;
|
|
|
|
stop_c:
|
|
nxt_state = stop_d;
|
|
|
|
stop_d:
|
|
begin
|
|
nxt_state = idle;
|
|
icmd_ack = 1'b1;
|
|
end
|
|
|
|
// read
|
|
rd_a:
|
|
nxt_state = rd_b;
|
|
|
|
rd_b:
|
|
nxt_state = rd_c;
|
|
|
|
rd_c:
|
|
begin
|
|
nxt_state = rd_d;
|
|
store_sda = 1'b1;
|
|
end
|
|
|
|
rd_d:
|
|
begin
|
|
nxt_state = idle;
|
|
icmd_ack = 1'b1;
|
|
end
|
|
|
|
// write
|
|
wr_a:
|
|
nxt_state = wr_b;
|
|
|
|
wr_b:
|
|
nxt_state = wr_c;
|
|
|
|
wr_c:
|
|
nxt_state = wr_d;
|
|
|
|
wr_d:
|
|
begin
|
|
nxt_state = idle;
|
|
icmd_ack = 1'b1;
|
|
end
|
|
|
|
endcase
|
|
end
|
|
|
|
|
|
// generate registers
|
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (!nReset)
|
if (!nReset)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= #1 1'b0;
|
dout <= #1 1'b0;
|
dout <= #1 1'b0;
|
|
scl_oen <= #1 1'b1;
|
|
sda_oen <= #1 1'b1;
|
end
|
end
|
else if (rst)
|
else if (rst)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= #1 1'b0;
|
dout <= #1 1'b0;
|
dout <= #1 1'b0;
|
|
scl_oen <= #1 1'b1;
|
|
sda_oen <= #1 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
|
|
if (clk_en)
|
if (clk_en)
|
|
case (c_state) // synopsis full_case parallel_case
|
|
// idle state
|
|
idle:
|
begin
|
begin
|
c_state <= #1 nxt_state;
|
case (cmd) // synopsis full_case parallel_case
|
if (store_sda)
|
`I2C_CMD_START:
|
dout <= #1 sSDA;
|
c_state <= #1 start_a;
|
end
|
|
|
|
cmd_ack <= #1 icmd_ack && clk_en;
|
`I2C_CMD_STOP:
|
end
|
c_state <= #1 stop_a;
|
|
|
//
|
`I2C_CMD_WRITE:
|
// convert states to SCL and SDA signals
|
c_state <= #1 wr_a;
|
//
|
|
|
|
// assign scl and sda output (always gnd)
|
`I2C_CMD_READ:
|
assign scl_o = 1'b0;
|
c_state <= #1 rd_a;
|
assign sda_o = 1'b0;
|
|
|
|
// assign scl and sda output_enables
|
default:
|
always @(posedge clk or negedge nReset)
|
c_state <= #1 idle;
|
if (!nReset)
|
endcase
|
begin
|
|
scl_oen <= #1 1'b1;
|
|
sda_oen <= #1 1'b1;
|
|
end
|
|
else if (rst)
|
|
begin
|
|
scl_oen <= #1 1'b1;
|
|
sda_oen <= #1 1'b1;
|
|
end
|
|
else if (clk_en)
|
|
case (c_state) // synopsis full_case parallel_case
|
|
|
|
// idle state
|
|
idle:
|
|
begin
|
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
sda_oen <= #1 sda_oen; // keep SDA in same state
|
sda_oen <= #1 sda_oen; // keep SDA in same state
|
end
|
end
|
|
|
// start
|
// start
|
start_a:
|
start_a:
|
begin
|
begin
|
|
c_state <= #1 start_b;
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= #1 1'b1; // set SDA high
|
end
|
end
|
|
|
start_b:
|
start_b:
|
begin
|
begin
|
|
c_state <= #1 start_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA high
|
sda_oen <= #1 1'b1; // keep SDA high
|
end
|
end
|
|
|
start_c:
|
start_c:
|
begin
|
begin
|
|
c_state <= #1 start_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
|
end
|
end
|
|
|
start_d:
|
start_d:
|
begin
|
begin
|
|
c_state <= #1 start_e;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
end
|
end
|
|
|
start_e:
|
start_e:
|
begin
|
begin
|
|
c_state <= #1 idle;
|
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
end
|
end
|
|
|
// stop
|
// stop
|
stop_a:
|
stop_a:
|
begin
|
begin
|
|
c_state <= #1 stop_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
|
end
|
end
|
|
|
stop_b:
|
stop_b:
|
begin
|
begin
|
|
c_state <= #1 stop_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
end
|
end
|
|
|
stop_c:
|
stop_c:
|
begin
|
begin
|
|
c_state <= #1 stop_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
end
|
end
|
|
|
stop_d:
|
stop_d:
|
begin
|
begin
|
|
c_state <= #1 idle;
|
|
cmd_ack <= #1 clk_en;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= #1 1'b1; // set SDA high
|
end
|
end
|
|
|
//write
|
// read
|
wr_a:
|
rd_a:
|
begin
|
begin
|
|
c_state <= #1 rd_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 din; // set SDA
|
sda_oen <= #1 1'b1; // tri-state SDA
|
end
|
end
|
|
|
wr_b:
|
rd_b:
|
begin
|
begin
|
|
c_state <= #1 rd_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 din; // keep SDA
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
end
|
end
|
|
|
wr_c:
|
rd_c:
|
begin
|
begin
|
|
c_state <= #1 rd_d;
|
|
dout <= #1 sSDA;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 din;
|
sda_oen <= #1 1'b1;
|
end
|
end
|
|
|
wr_d:
|
rd_d:
|
begin
|
begin
|
|
c_state <= #1 idle;
|
|
cmd_ack <= #1 clk_en;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 din;
|
sda_oen <= #1 1'b1;
|
end
|
end
|
|
|
// read
|
// write
|
rd_a:
|
wr_a:
|
begin
|
begin
|
|
c_state <= #1 wr_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b1; // tri-state SDA
|
sda_oen <= #1 din; // set SDA
|
end
|
end
|
|
|
rd_b:
|
wr_b:
|
begin
|
begin
|
|
c_state <= #1 wr_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= #1 din; // keep SDA
|
end
|
end
|
|
|
rd_c:
|
wr_c:
|
begin
|
begin
|
|
c_state <= #1 wr_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 din;
|
end
|
end
|
|
|
rd_d:
|
wr_d:
|
begin
|
begin
|
|
c_state <= #1 idle;
|
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 din;
|
end
|
end
|
|
|
endcase
|
endcase
|
|
end
|
|
|
|
|
|
// assign scl and sda output (always gnd)
|
|
assign scl_o = 1'b0;
|
|
assign sda_o = 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|
