/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
|
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// Author: Richard Herveille ////
|
//// Author: Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// www.asics.ws ////
|
//// www.asics.ws ////
|
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// Copyright (C) 2001 Richard Herveille ////
|
//// richard@asics.ws ////
|
//// richard@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// POSSIBILITY OF SUCH DAMAGE. ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
|
// $Id: i2c_master_bit_ctrl.v,v 1.14 2009-01-20 10:25:29 rherveille Exp $
|
//
|
//
|
// $Date: 2009-01-20 10:25:29 $
|
// $Date: 2009-01-20 10:25:29 $
|
// $Revision: 1.14 $
|
// $Revision: 1.14 $
|
// $Author: rherveille $
|
// $Author: rherveille $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: $
|
|
// Revision 1.14 2009/01/20 10:25:29 rherveille
|
|
// Added clock synchronization logic
|
|
// Fixed slave_wait signal
|
|
//
|
// Revision 1.13 2009/01/19 20:29:26 rherveille
|
// Revision 1.13 2009/01/19 20:29:26 rherveille
|
// Fixed synopsys miss spell (synopsis)
|
// Fixed synopsys miss spell (synopsis)
|
// Fixed cr[0] register width
|
// Fixed cr[0] register width
|
// Fixed ! usage instead of ~
|
// Fixed ! usage instead of ~
|
// Fixed bit controller parameter width to 18bits
|
// Fixed bit controller parameter width to 18bits
|
//
|
//
|
// Revision 1.12 2006/09/04 09:08:13 rherveille
|
// Revision 1.12 2006/09/04 09:08:13 rherveille
|
// fixed short scl high pulse after clock stretch
|
// fixed short scl high pulse after clock stretch
|
// fixed slave model not returning correct '(n)ack' signal
|
// fixed slave model not returning correct '(n)ack' signal
|
//
|
//
|
// Revision 1.11 2004/05/07 11:02:26 rherveille
|
// Revision 1.11 2004/05/07 11:02:26 rherveille
|
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
|
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
|
//
|
//
|
// Revision 1.10 2003/08/09 07:01:33 rherveille
|
// Revision 1.10 2003/08/09 07:01:33 rherveille
|
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
// Fixed a potential bug in the byte controller's host-acknowledge generation.
|
// Fixed a potential bug in the byte controller's host-acknowledge generation.
|
//
|
//
|
// Revision 1.9 2003/03/10 14:26:37 rherveille
|
// Revision 1.9 2003/03/10 14:26:37 rherveille
|
// Fixed cmd_ack generation item (no bug).
|
// Fixed cmd_ack generation item (no bug).
|
//
|
//
|
// Revision 1.8 2003/02/05 00:06:10 rherveille
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// Revision 1.8 2003/02/05 00:06:10 rherveille
|
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
|
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
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//
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//
|
// Revision 1.7 2002/12/26 16:05:12 rherveille
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// Revision 1.7 2002/12/26 16:05:12 rherveille
|
// Small code simplifications
|
// Small code simplifications
|
//
|
//
|
// Revision 1.6 2002/12/26 15:02:32 rherveille
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// Revision 1.6 2002/12/26 15:02:32 rherveille
|
// Core is now a Multimaster I2C controller
|
// Core is now a Multimaster I2C controller
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//
|
//
|
// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Revision 1.5 2002/11/30 22:24:40 rherveille
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// Cleaned up code
|
// Cleaned up code
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//
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//
|
// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Revision 1.4 2002/10/30 18:10:07 rherveille
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// Fixed some reported minor start/stop generation timing issuess.
|
// Fixed some reported minor start/stop generation timing issuess.
|
//
|
//
|
// Revision 1.3 2002/06/15 07:37:03 rherveille
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// Revision 1.3 2002/06/15 07:37:03 rherveille
|
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
//
|
//
|
// Revision 1.2 2001/11/05 11:59:25 rherveille
|
// Revision 1.2 2001/11/05 11:59:25 rherveille
|
// Fixed wb_ack_o generation bug.
|
// Fixed wb_ack_o generation bug.
|
// Fixed bug in the byte_controller statemachine.
|
// Fixed bug in the byte_controller statemachine.
|
// Added headers.
|
// Added headers.
|
//
|
//
|
|
|
//
|
//
|
/////////////////////////////////////
|
/////////////////////////////////////
|
// Bit controller section
|
// Bit controller section
|
/////////////////////////////////////
|
/////////////////////////////////////
|
//
|
//
|
// Translate simple commands into SCL/SDA transitions
|
// Translate simple commands into SCL/SDA transitions
|
// Each command has 5 states, A/B/C/D/idle
|
// Each command has 5 states, A/B/C/D/idle
|
//
|
//
|
// start: SCL ~~~~~~~~~~\____
|
// start: SCL ~~~~~~~~~~\____
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// SDA ~~~~~~~~\______
|
// SDA ~~~~~~~~\______
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
// repstart SCL ____/~~~~\___
|
// repstart SCL ____/~~~~\___
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// SDA __/~~~\______
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// SDA __/~~~\______
|
// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
|
//
|
// stop SCL ____/~~~~~~~~
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// stop SCL ____/~~~~~~~~
|
// SDA ==\____/~~~~~
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// SDA ==\____/~~~~~
|
// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
|
//
|
//- write SCL ____/~~~~\____
|
//- write SCL ____/~~~~\____
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// SDA ==X=========X=
|
// SDA ==X=========X=
|
// x | A | B | C | D | i
|
// x | A | B | C | D | i
|
//
|
//
|
//- read SCL ____/~~~~\____
|
//- read SCL ____/~~~~\____
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// SDA XXXX=====XXXX
|
// SDA XXXX=====XXXX
|
// x | A | B | C | D | i
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// x | A | B | C | D | i
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//
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//
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|
|
// Timing: Normal mode Fast mode
|
// Timing: Normal mode Fast mode
|
///////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////
|
// Fscl 100KHz 400KHz
|
// Fscl 100KHz 400KHz
|
// Th_scl 4.0us 0.6us High period of SCL
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// Th_scl 4.0us 0.6us High period of SCL
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// Tl_scl 4.7us 1.3us Low period of SCL
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// Tl_scl 4.7us 1.3us Low period of SCL
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// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tsu:sto 4.0us 0.6us setup time for a stop conditon
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// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
|
|
`include "i2c_master_defines.v"
|
`include "i2c_master_defines.v"
|
|
|
module i2c_master_bit_ctrl(
|
module i2c_master_bit_ctrl(
|
clk, rst, nReset,
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input clk, // system clock
|
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
|
input rst, // synchronous active high reset
|
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
|
input nReset, // asynchronous active low reset
|
|
input ena, // core enable signal
|
|
|
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input [15:0] clk_cnt, // clock prescale value
|
|
|
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input [ 3:0] cmd, // command (from byte controller)
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|
output reg cmd_ack, // command complete acknowledge
|
|
output reg busy, // i2c bus busy
|
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output reg al, // i2c bus arbitration lost
|
|
|
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input din,
|
|
output reg dout,
|
|
|
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input scl_i, // i2c clock line input
|
|
output scl_o, // i2c clock line output
|
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output reg scl_oen, // i2c clock line output enable (active low)
|
|
input sda_i, // i2c data line input
|
|
output sda_o, // i2c data line output
|
|
output reg sda_oen // i2c data line output enable (active low)
|
);
|
);
|
|
|
//
|
|
// inputs & outputs
|
|
//
|
|
input clk;
|
|
input rst;
|
|
input nReset;
|
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input ena; // core enable signal
|
|
|
|
input [15:0] clk_cnt; // clock prescale value
|
|
|
|
input [3:0] cmd;
|
|
output cmd_ack; // command complete acknowledge
|
|
reg cmd_ack;
|
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output busy; // i2c bus busy
|
|
reg busy;
|
|
output al; // i2c bus arbitration lost
|
|
reg al;
|
|
|
|
input din;
|
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output dout;
|
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reg dout;
|
|
|
|
// I2C lines
|
|
input scl_i; // i2c clock line input
|
|
output scl_o; // i2c clock line output
|
|
output scl_oen; // i2c clock line output enable (active low)
|
|
reg scl_oen;
|
|
input sda_i; // i2c data line input
|
|
output sda_o; // i2c data line output
|
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output sda_oen; // i2c data line output enable (active low)
|
|
reg sda_oen;
|
|
|
|
|
|
//
|
//
|
// variable declarations
|
// variable declarations
|
//
|
//
|
|
|
reg sSCL, sSDA; // synchronized SCL and SDA inputs
|
reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
|
|
reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
|
|
reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
|
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
|
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
|
reg dscl_oen; // delayed scl_oen
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reg dscl_oen; // delayed scl_oen
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reg sda_chk; // check SDA output (Multi-master arbitration)
|
reg sda_chk; // check SDA output (Multi-master arbitration)
|
reg clk_en; // clock generation signals
|
reg clk_en; // clock generation signals
|
reg slave_wait; // slave inserts wait states
|
reg slave_wait; // slave inserts wait states
|
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
|
|
reg [15:0] cnt; // clock divider counter (synthesis)
|
reg [15:0] cnt; // clock divider counter (synthesis)
|
|
reg [13:0] filter_cnt; // clock divider for filter
|
|
|
|
|
// state machine variable
|
// state machine variable
|
reg [17:0] c_state; // synopsys enum_state
|
reg [17:0] c_state; // synopsys enum_state
|
|
|
//
|
//
|
// module body
|
// module body
|
//
|
//
|
|
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
// delay scl_oen
|
// delay scl_oen
|
always @(posedge clk)
|
always @(posedge clk)
|
dscl_oen <= #1 scl_oen;
|
dscl_oen <= #1 scl_oen;
|
|
|
// slave_wait is asserted when master wants to drive SCL high, but the slave (another master) pulls it low
|
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
|
// slave_wait remains asserted until the slave (other master) releases SCL
|
// slave_wait remains asserted until the slave releases SCL
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (!nReset) slave_wait <= 1'b0;
|
if (!nReset) slave_wait <= 1'b0;
|
else slave_wait = (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
|
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
|
|
|
// master drives SCL high, but another master pulls it low
|
// master drives SCL high, but another master pulls it low
|
// master start counting down its low cycle now (clock synchronization)
|
// master start counting down its low cycle now (clock synchronization)
|
wire scl_sync = dSCL & ~sSCL & scl_oen;
|
wire scl_sync = dSCL & ~sSCL & scl_oen;
|
|
|
|
|
// generate clk enable signal
|
// generate clk enable signal
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if(~nReset)
|
if (~nReset)
|
begin
|
begin
|
cnt <= #1 16'h0;
|
cnt <= #1 16'h0;
|
clk_en <= #1 1'b1;
|
clk_en <= #1 1'b1;
|
end
|
end
|
else if (rst)
|
else if (rst || ~|cnt || !ena || scl_sync)
|
begin
|
|
cnt <= #1 16'h0;
|
|
clk_en <= #1 1'b1;
|
|
end
|
|
else if ( ~|cnt || !ena || scl_sync)
|
|
begin
|
begin
|
cnt <= #1 clk_cnt;
|
cnt <= #1 clk_cnt;
|
clk_en <= #1 1'b1;
|
clk_en <= #1 1'b1;
|
end
|
end
|
else if (slave_wait)
|
else if (slave_wait)
|
begin
|
begin
|
cnt <= #1 cnt;
|
cnt <= #1 cnt;
|
clk_en <= #1 1'b0;
|
clk_en <= #1 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cnt <= #1 cnt - 16'h1;
|
cnt <= #1 cnt - 16'h1;
|
clk_en <= #1 1'b0;
|
clk_en <= #1 1'b0;
|
end
|
end
|
|
|
|
|
// generate bus status controller
|
// generate bus status controller
|
reg sta_condition;
|
|
reg sto_condition;
|
|
|
|
// synchronize SCL and SDA inputs
|
// capture SDA and SCL
|
// reduce metastability risc
|
// reduce metastability risk
|
|
always @(posedge clk or negedge nReset)
|
|
if (!nReset)
|
|
begin
|
|
cSCL <= #1 2'b00;
|
|
cSDA <= #1 2'b00;
|
|
end
|
|
else if (rst)
|
|
begin
|
|
cSCL <= #1 2'b00;
|
|
cSDA <= #1 2'b00;
|
|
end
|
|
else
|
|
begin
|
|
cSCL <= {cSCL[0],scl_i};
|
|
cSDA <= {cSDA[0],sda_i};
|
|
end
|
|
|
|
|
|
// filter SCL and SDA signals; (attempt to) remove glitches
|
|
always @(posedge clk or negedge nReset)
|
|
if (!nReset ) filter_cnt <= 14'h0;
|
|
else if (rst || !ena ) filter_cnt <= 14'h0;
|
|
else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
|
|
else filter_cnt <= filter_cnt -1;
|
|
|
|
|
|
always @(posedge clk or negedge nReset)
|
|
if (!nReset)
|
|
begin
|
|
fSCL <= 3'b111;
|
|
fSDA <= 3'b111;
|
|
end
|
|
else if (rst)
|
|
begin
|
|
fSCL <= 3'b111;
|
|
fSDA <= 3'b111;
|
|
end
|
|
else if (~|filter_cnt)
|
|
begin
|
|
fSCL <= {fSCL[1:0],cSCL[1]};
|
|
fSDA <= {fSDA[1:0],cSDA[1]};
|
|
end
|
|
|
|
|
|
// generate filtered SCL and SDA signals
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (~nReset)
|
if (~nReset)
|
begin
|
begin
|
sSCL <= #1 1'b1;
|
sSCL <= #1 1'b1;
|
sSDA <= #1 1'b1;
|
sSDA <= #1 1'b1;
|
|
|
dSCL <= #1 1'b1;
|
dSCL <= #1 1'b1;
|
dSDA <= #1 1'b1;
|
dSDA <= #1 1'b1;
|
end
|
end
|
else if (rst)
|
else if (rst)
|
begin
|
begin
|
sSCL <= #1 1'b1;
|
sSCL <= #1 1'b1;
|
sSDA <= #1 1'b1;
|
sSDA <= #1 1'b1;
|
|
|
dSCL <= #1 1'b1;
|
dSCL <= #1 1'b1;
|
dSDA <= #1 1'b1;
|
dSDA <= #1 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sSCL <= #1 scl_i;
|
sSCL <= #1 &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
|
sSDA <= #1 sda_i;
|
sSDA <= #1 &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
|
|
|
dSCL <= #1 sSCL;
|
dSCL <= #1 sSCL;
|
dSDA <= #1 sSDA;
|
dSDA <= #1 sSDA;
|
end
|
end
|
|
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect start condition => detect falling edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
// detect stop condition => detect rising edge on SDA while SCL is high
|
|
reg sta_condition;
|
|
reg sto_condition;
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (~nReset)
|
if (~nReset)
|
begin
|
begin
|
sta_condition <= #1 1'b0;
|
sta_condition <= #1 1'b0;
|
sto_condition <= #1 1'b0;
|
sto_condition <= #1 1'b0;
|
end
|
end
|
else if (rst)
|
else if (rst)
|
begin
|
begin
|
sta_condition <= #1 1'b0;
|
sta_condition <= #1 1'b0;
|
sto_condition <= #1 1'b0;
|
sto_condition <= #1 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
sta_condition <= #1 ~sSDA & dSDA & sSCL;
|
sta_condition <= #1 ~sSDA & dSDA & sSCL;
|
sto_condition <= #1 sSDA & ~dSDA & sSCL;
|
sto_condition <= #1 sSDA & ~dSDA & sSCL;
|
end
|
end
|
|
|
|
|
// generate i2c bus busy signal
|
// generate i2c bus busy signal
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if(!nReset)
|
if (!nReset) busy <= #1 1'b0;
|
busy <= #1 1'b0;
|
else if (rst ) busy <= #1 1'b0;
|
else if (rst)
|
else busy <= #1 (sta_condition | busy) & ~sto_condition;
|
busy <= #1 1'b0;
|
|
else
|
|
busy <= #1 (sta_condition | busy) & ~sto_condition;
|
|
|
|
// generate arbitration lost signal
|
// generate arbitration lost signal
|
// aribitration lost when:
|
// aribitration lost when:
|
// 1) master drives SDA high, but the i2c bus is low
|
// 1) master drives SDA high, but the i2c bus is low
|
// 2) stop detected while not requested
|
// 2) stop detected while not requested
|
reg cmd_stop;
|
reg cmd_stop;
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (~nReset)
|
if (~nReset)
|
cmd_stop <= #1 1'b0;
|
cmd_stop <= #1 1'b0;
|
else if (rst)
|
else if (rst)
|
cmd_stop <= #1 1'b0;
|
cmd_stop <= #1 1'b0;
|
else if (clk_en)
|
else if (clk_en)
|
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
|
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
|
|
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (~nReset)
|
if (~nReset)
|
al <= #1 1'b0;
|
al <= #1 1'b0;
|
else if (rst)
|
else if (rst)
|
al <= #1 1'b0;
|
al <= #1 1'b0;
|
else
|
else
|
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
|
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
|
|
|
|
|
// generate dout signal (store SDA on rising edge of SCL)
|
// generate dout signal (store SDA on rising edge of SCL)
|
always @(posedge clk)
|
always @(posedge clk)
|
if(sSCL & ~dSCL)
|
if (sSCL & ~dSCL) dout <= #1 sSDA;
|
dout <= #1 sSDA;
|
|
|
|
// generate statemachine
|
// generate statemachine
|
|
|
// nxt_state decoder
|
// nxt_state decoder
|
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
|
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
|
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
|
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
|
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
|
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
|
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
|
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
|
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
|
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
|
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
|
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
|
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
|
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
|
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
|
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
|
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
|
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
|
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
|
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
|
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
|
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
|
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
|
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
|
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
|
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
|
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
|
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
|
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
|
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
|
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
|
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
|
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
|
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
|
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
|
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
|
|
|
always @(posedge clk or negedge nReset)
|
always @(posedge clk or negedge nReset)
|
if (!nReset)
|
if (!nReset)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= #1 1'b0;
|
scl_oen <= #1 1'b1;
|
scl_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_chk <= #1 1'b0;
|
sda_chk <= #1 1'b0;
|
end
|
end
|
else if (rst | al)
|
else if (rst | al)
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b0;
|
cmd_ack <= #1 1'b0;
|
scl_oen <= #1 1'b1;
|
scl_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_oen <= #1 1'b1;
|
sda_chk <= #1 1'b0;
|
sda_chk <= #1 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
|
|
if (clk_en)
|
if (clk_en)
|
case (c_state) // synopsys full_case parallel_case
|
case (c_state) // synopsys full_case parallel_case
|
// idle state
|
// idle state
|
idle:
|
idle:
|
begin
|
begin
|
case (cmd) // synopsys full_case parallel_case
|
case (cmd) // synopsys full_case parallel_case
|
`I2C_CMD_START:
|
`I2C_CMD_START: c_state <= #1 start_a;
|
c_state <= #1 start_a;
|
`I2C_CMD_STOP: c_state <= #1 stop_a;
|
|
`I2C_CMD_WRITE: c_state <= #1 wr_a;
|
`I2C_CMD_STOP:
|
`I2C_CMD_READ: c_state <= #1 rd_a;
|
c_state <= #1 stop_a;
|
default: c_state <= #1 idle;
|
|
|
`I2C_CMD_WRITE:
|
|
c_state <= #1 wr_a;
|
|
|
|
`I2C_CMD_READ:
|
|
c_state <= #1 rd_a;
|
|
|
|
default:
|
|
c_state <= #1 idle;
|
|
endcase
|
endcase
|
|
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
sda_oen <= #1 sda_oen; // keep SDA in same state
|
sda_oen <= #1 sda_oen; // keep SDA in same state
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// start
|
// start
|
start_a:
|
start_a:
|
begin
|
begin
|
c_state <= #1 start_b;
|
c_state <= #1 start_b;
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
scl_oen <= #1 scl_oen; // keep SCL in same state
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_b:
|
start_b:
|
begin
|
begin
|
c_state <= #1 start_c;
|
c_state <= #1 start_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA high
|
sda_oen <= #1 1'b1; // keep SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_c:
|
start_c:
|
begin
|
begin
|
c_state <= #1 start_d;
|
c_state <= #1 start_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_d:
|
start_d:
|
begin
|
begin
|
c_state <= #1 start_e;
|
c_state <= #1 start_e;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
start_e:
|
start_e:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// stop
|
// stop
|
stop_a:
|
stop_a:
|
begin
|
begin
|
c_state <= #1 stop_b;
|
c_state <= #1 stop_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_oen <= #1 1'b0; // set SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_b:
|
stop_b:
|
begin
|
begin
|
c_state <= #1 stop_c;
|
c_state <= #1 stop_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_c:
|
stop_c:
|
begin
|
begin
|
c_state <= #1 stop_d;
|
c_state <= #1 stop_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_oen <= #1 1'b0; // keep SDA low
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
stop_d:
|
stop_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_oen <= #1 1'b1; // set SDA high
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// read
|
// read
|
rd_a:
|
rd_a:
|
begin
|
begin
|
c_state <= #1 rd_b;
|
c_state <= #1 rd_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 1'b1; // tri-state SDA
|
sda_oen <= #1 1'b1; // tri-state SDA
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_b:
|
rd_b:
|
begin
|
begin
|
c_state <= #1 rd_c;
|
c_state <= #1 rd_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_c:
|
rd_c:
|
begin
|
begin
|
c_state <= #1 rd_d;
|
c_state <= #1 rd_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
rd_d:
|
rd_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
sda_chk <= #1 1'b0; // don't check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output
|
end
|
end
|
|
|
// write
|
// write
|
wr_a:
|
wr_a:
|
begin
|
begin
|
c_state <= #1 wr_b;
|
c_state <= #1 wr_b;
|
scl_oen <= #1 1'b0; // keep SCL low
|
scl_oen <= #1 1'b0; // keep SCL low
|
sda_oen <= #1 din; // set SDA
|
sda_oen <= #1 din; // set SDA
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
wr_b:
|
wr_b:
|
begin
|
begin
|
c_state <= #1 wr_c;
|
c_state <= #1 wr_c;
|
scl_oen <= #1 1'b1; // set SCL high
|
scl_oen <= #1 1'b1; // set SCL high
|
sda_oen <= #1 din; // keep SDA
|
sda_oen <= #1 din; // keep SDA
|
sda_chk <= #1 1'b1; // check SDA output
|
sda_chk <= #1 1'b0; // don't check SDA output yet
|
|
// allow some time for SDA and SCL to settle
|
end
|
end
|
|
|
wr_c:
|
wr_c:
|
begin
|
begin
|
c_state <= #1 wr_d;
|
c_state <= #1 wr_d;
|
scl_oen <= #1 1'b1; // keep SCL high
|
scl_oen <= #1 1'b1; // keep SCL high
|
sda_oen <= #1 din;
|
sda_oen <= #1 din;
|
sda_chk <= #1 1'b1; // check SDA output
|
sda_chk <= #1 1'b1; // check SDA output
|
end
|
end
|
|
|
wr_d:
|
wr_d:
|
begin
|
begin
|
c_state <= #1 idle;
|
c_state <= #1 idle;
|
cmd_ack <= #1 1'b1;
|
cmd_ack <= #1 1'b1;
|
scl_oen <= #1 1'b0; // set SCL low
|
scl_oen <= #1 1'b0; // set SCL low
|
sda_oen <= #1 din;
|
sda_oen <= #1 din;
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
end
|
end
|
|
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
// assign scl and sda output (always gnd)
|
// assign scl and sda output (always gnd)
|
assign scl_o = 1'b0;
|
assign scl_o = 1'b0;
|
assign sda_o = 1'b0;
|
assign sda_o = 1'b0;
|
|
|
endmodule
|
endmodule
|
|
|
