//
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//
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// WISHBONE revB2 compiant I2C master core
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// WISHBONE revB2 compiant I2C master core
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//
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//
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// author: Richard Herveille
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// author: Richard Herveille
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// rev. 0.1 26-08-2001. Iinitial Verilog release
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// rev. 0.1 26-08-2001. Iinitial Verilog release
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "i2c_master_defines.v"
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`include "i2c_master_defines.v"
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module i2c_master_top(
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module i2c_master_top(
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wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
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wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
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scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
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scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
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// parameters
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// parameters
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parameter ARST_LVL = 1'b0; // asynchronous reset level
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parameter ARST_LVL = 1'b0; // asynchronous reset level
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//
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//
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// inputs & outputs
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// inputs & outputs
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//
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//
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// wishbone signals
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// wishbone signals
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input wb_clk_i; // master clock input
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input wb_clk_i; // master clock input
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input wb_rst_i; // synchronous active high reset
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input wb_rst_i; // synchronous active high reset
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input arst_i; // asynchronous reset
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input arst_i; // asynchronous reset
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input [2:0] wb_adr_i; // lower address bits
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input [2:0] wb_adr_i; // lower address bits
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input [7:0] wb_dat_i; // databus input
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input [7:0] wb_dat_i; // databus input
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output [7:0] wb_dat_o; // databus output
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output [7:0] wb_dat_o; // databus output
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reg [7:0] wb_dat_o;
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reg [7:0] wb_dat_o;
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input wb_we_i; // write enable input
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input wb_we_i; // write enable input
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input wb_stb_i; // stobe/core select signal
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input wb_stb_i; // stobe/core select signal
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input wb_cyc_i; // valid bus cycle input
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input wb_cyc_i; // valid bus cycle input
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output wb_ack_o; // bus cycle acknowledge output
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output wb_ack_o; // bus cycle acknowledge output
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output wb_inta_o; // interrupt request signal output
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output wb_inta_o; // interrupt request signal output
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reg wb_inta_o;
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reg wb_inta_o;
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// I2C signals
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// I2C signals
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// i2c clock line
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// i2c clock line
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input scl_pad_i; // SCL-line input
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input scl_pad_i; // SCL-line input
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output scl_pad_o; // SCL-line output (always 1'b0)
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output scl_pad_o; // SCL-line output (always 1'b0)
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output scl_padoen_o; // SCL-line output enable (active low)
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output scl_padoen_o; // SCL-line output enable (active low)
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// i2c data line
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// i2c data line
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input sda_pad_i; // SDA-line input
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input sda_pad_i; // SDA-line input
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output sda_pad_o; // SDA-line output (always 1'b0)
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output sda_pad_o; // SDA-line output (always 1'b0)
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output sda_padoen_o; // SDA-line output enable (active low)
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output sda_padoen_o; // SDA-line output enable (active low)
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//
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//
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// variable declarations
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// variable declarations
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//
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//
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// registers
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// registers
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reg [15:0] prer; // clock prescale register
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reg [15:0] prer; // clock prescale register
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reg [ 7:0] ctr; // control register
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reg [ 7:0] ctr; // control register
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reg [ 7:0] txr; // transmit register
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reg [ 7:0] txr; // transmit register
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wire [ 7:0] rxr; // receive register
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wire [ 7:0] rxr; // receive register
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reg [ 7:0] cr; // command register
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reg [ 7:0] cr; // command register
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wire [ 7:0] sr; // status register
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wire [ 7:0] sr; // status register
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// done signal: command completed, clear command register
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// done signal: command completed, clear command register
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wire done;
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wire done;
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// core enable signal
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// core enable signal
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wire core_en;
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wire core_en;
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wire ien;
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// status register signals
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// status register signals
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wire irxack;
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wire irxack;
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reg rxack; // received aknowledge from slave
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reg rxack; // received aknowledge from slave
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reg tip; // transfer in progress
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reg tip; // transfer in progress
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reg irq_flag; // interrupt pending flag
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reg irq_flag; // interrupt pending flag
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wire i2c_busy; // bus busy (start signal detected)
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wire i2c_busy; // bus busy (start signal detected)
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//
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//
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// module body
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// module body
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//
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//
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// generate internal reset
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// generate internal reset
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wire rst_i = arst_i ^ ARST_LVL;
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wire rst_i = arst_i ^ ARST_LVL;
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// generate acknowledge output signal
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// generate acknowledge output signal
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assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored
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assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored
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// assign DAT_O
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// assign DAT_O
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always@(wb_adr_i or prer or ctr or txr or cr or rxr or sr)
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always@(wb_adr_i or prer or ctr or txr or cr or rxr or sr)
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begin
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begin
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case (wb_adr_i) // synopsis full_case parallel_case
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case (wb_adr_i) // synopsis full_case parallel_case
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3'b000: wb_dat_o = prer[ 7:0];
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3'b000: wb_dat_o = prer[ 7:0];
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3'b001: wb_dat_o = prer[15:8];
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3'b001: wb_dat_o = prer[15:8];
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3'b010: wb_dat_o = ctr;
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3'b010: wb_dat_o = ctr;
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3'b011: wb_dat_o = rxr; // write is transmit register (txr)
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3'b011: wb_dat_o = rxr; // write is transmit register (txr)
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3'b100: wb_dat_o = sr; // write is command register (cr)
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3'b100: wb_dat_o = sr; // write is command register (cr)
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3'b101: wb_dat_o = txr;
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3'b101: wb_dat_o = txr;
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3'b110: wb_dat_o = cr;
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3'b110: wb_dat_o = cr;
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endcase
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endcase
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end
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end
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// generate registers
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// generate registers
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always@(posedge wb_clk_i or negedge rst_i)
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always@(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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begin
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begin
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prer <= #1 16'h0;
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prer <= #1 16'h0;
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ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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cr <= #1 8'h0;
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cr <= #1 8'h0;
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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begin
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begin
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prer <= #1 16'h0;
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prer <= #1 16'h0;
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ctr <= #1 8'h0;
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ctr <= #1 8'h0;
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txr <= #1 8'h0;
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txr <= #1 8'h0;
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cr <= #1 8'h0;
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cr <= #1 8'h0;
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end
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end
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else
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else
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if (wb_cyc_i && wb_stb_i && wb_we_i)
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if (wb_cyc_i && wb_stb_i && wb_we_i)
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begin
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begin
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if (!wb_adr_i[2])
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if (!wb_adr_i[2])
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case (wb_adr_i[1:0]) // synopsis full_case parallel_case
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case (wb_adr_i[1:0]) // synopsis full_case parallel_case
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2'b00 : prer [ 7:0] <= #1 wb_dat_i;
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2'b00 : prer [ 7:0] <= #1 wb_dat_i;
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2'b01 : prer [15:8] <= #1 wb_dat_i;
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2'b01 : prer [15:8] <= #1 wb_dat_i;
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2'b10 : ctr <= #1 wb_dat_i;
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2'b10 : ctr <= #1 wb_dat_i;
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2'b11 : txr <= #1 wb_dat_i;
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2'b11 : txr <= #1 wb_dat_i;
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endcase
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endcase
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else
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else
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if (core_en && (wb_adr_i[1:0] == 2'b00) ) // only take new commands when i2c core enabled, pending commands are finished
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if (core_en && (wb_adr_i[1:0] == 2'b00) ) // only take new commands when i2c core enabled, pending commands are finished
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cr <= #1 wb_dat_i;
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cr <= #1 wb_dat_i;
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end
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end
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else
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else
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begin
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begin
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if (done)
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if (done)
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cr[7:4] <= #1 4'h0; // clear command bits when done
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cr[7:4] <= #1 4'h0; // clear command bits when done
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cr[2:1] <= #1 2'b00; // reserved bits
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cr[2:1] <= #1 2'b00; // reserved bits
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cr[0] <= #1 cr[0] && irq_flag; // clear when irq_flag cleared
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cr[0] <= #1 cr[0] && irq_flag; // clear when irq_flag cleared
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end
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end
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// decode command register
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// decode command register
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wire sta = cr[7];
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wire sta = cr[7];
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wire sto = cr[6];
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wire sto = cr[6];
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wire rd = cr[5];
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wire rd = cr[5];
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wire wr = cr[4];
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wire wr = cr[4];
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wire ack = cr[3];
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wire ack = cr[3];
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wire iack = cr[0];
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wire iack = cr[0];
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// decode control register
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// decode control register
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assign core_en = ctr[7];
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assign core_en = ctr[7];
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assign ien = ctr[6];
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// hookup byte controller block
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// hookup byte controller block
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i2c_master_byte_ctrl byte_controller (
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i2c_master_byte_ctrl byte_controller (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.nReset(rst_i),
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.nReset(rst_i),
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.ena(core_en),
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.ena(core_en),
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.clk_cnt(prer),
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.clk_cnt(prer),
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.start(sta),
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.start(sta),
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.stop(sto),
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.stop(sto),
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.read(rd),
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.read(rd),
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.write(wr),
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.write(wr),
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.ack_in(ack),
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.ack_in(ack),
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.din(txr),
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.din(txr),
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.cmd_ack(done),
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.cmd_ack(done),
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.ack_out(irxack),
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.ack_out(irxack),
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.dout(rxr),
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.dout(rxr),
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.i2c_busy(i2c_busy),
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.i2c_busy(i2c_busy),
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.scl_i(scl_pad_i),
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.scl_i(scl_pad_i),
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.scl_o(scl_pad_o),
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.scl_o(scl_pad_o),
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.scl_oen(scl_padoen_o),
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.scl_oen(scl_padoen_o),
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.sda_i(sda_pad_i),
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.sda_i(sda_pad_i),
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.sda_o(sda_pad_o),
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.sda_o(sda_pad_o),
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.sda_oen(sda_padoen_o)
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.sda_oen(sda_padoen_o)
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);
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);
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// status register block + interrupt request signal
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// status register block + interrupt request signal
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always@(posedge wb_clk_i or negedge rst_i)
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always@(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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begin
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begin
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rxack <= #1 1'b0;
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rxack <= #1 1'b0;
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tip <= #1 1'b0;
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tip <= #1 1'b0;
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irq_flag <= #1 1'b0;
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irq_flag <= #1 1'b0;
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end
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end
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else if (wb_rst_i)
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else if (wb_rst_i)
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begin
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begin
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rxack <= #1 1'b0;
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rxack <= #1 1'b0;
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tip <= #1 1'b0;
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tip <= #1 1'b0;
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irq_flag <= #1 1'b0;
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irq_flag <= #1 1'b0;
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end
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end
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else
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else
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begin
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begin
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rxack <= #1 irxack;
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rxack <= #1 irxack;
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tip <= #1 (rd || wr);
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tip <= #1 (rd || wr);
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irq_flag <= #1 (done || irq_flag) && !iack; // interrupt request flag is always generated
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irq_flag <= #1 (done || irq_flag) && !iack; // interrupt request flag is always generated
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end
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end
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// generate interrupt request signals
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// generate interrupt request signals
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always@(posedge wb_clk_i or negedge rst_i)
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always@(posedge wb_clk_i or negedge rst_i)
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if (!rst_i)
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if (!rst_i)
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wb_inta_o <= #1 1'b0;
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wb_inta_o <= #1 1'b0;
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else if (wb_rst_i)
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else if (wb_rst_i)
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wb_inta_o <= #1 1'b0;
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wb_inta_o <= #1 1'b0;
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else
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else
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wb_inta_o <= #1 irq_flag && ctr[6]; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
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// assign status register bits
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// assign status register bits
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assign sr[7] = rxack;
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assign sr[7] = rxack;
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assign sr[6] = i2c_busy;
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assign sr[6] = i2c_busy;
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assign sr[5:2] = 4'h0; // reserved
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assign sr[5:2] = 4'h0; // reserved
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assign sr[1] = tip;
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assign sr[1] = tip;
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assign sr[0] = irq_flag;
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assign sr[0] = irq_flag;
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endmodule
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endmodule
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