URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [sim/] [i2c_verilog/] [run/] [run] - Diff between revs 61 and 68

Rev 61	Rev 68
`#!/bin/csh`	`#!/bin/csh`

`set i2c = ../../..`	`set i2c = ../../..`
`set bench = $i2c/bench`	`set bench = $i2c/bench`
`set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves`	`set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves`

`ncverilog \`	`ncverilog \`
`\`	`\`
`+access+rwc \`	`+access+rwc \`
`+define+WAVES \`	`+define+WAVES \`
`\`	`\`
`+incdir+$bench/verilog \`	`+incdir+$bench/verilog \`
`+incdir+$i2c/rtl/verilog \`	`+incdir+$i2c/rtl/verilog \`
`\`	`\`
`$i2c/rtl/verilog/i2c_master_bit_ctrl.v \`	`$i2c/rtl/verilog/i2c_master_bit_ctrl.v \`
`$i2c/rtl/verilog/i2c_master_byte_ctrl.v \`	`$i2c/rtl/verilog/i2c_master_byte_ctrl.v \`
`$i2c/rtl/verilog/i2c_master_top.v \`	`$i2c/rtl/verilog/i2c_master_top.v \`
`\`	`\`
`$bench/verilog/i2c_slave_model.v \`	`$bench/verilog/i2c_slave_model.v \`
`$bench/verilog/wb_master_model.v \`	`$bench/verilog/wb_master_model.v \`
`$bench/verilog/tst_bench_top.v`	`$bench/verilog/tst_bench_top.v`