//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module
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module
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i2c_to_wb_top
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i2c_to_wb_top
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#(
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#(
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parameter DW = 32,
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parameter DW = 32,
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parameter AW = 8
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parameter AW = 8
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)
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)
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(
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(
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input i2c_data_in,
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input i2c_data_in,
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input i2c_clk_in,
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input i2c_clk_in,
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output i2c_data_out,
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output i2c_data_out,
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output i2c_clk_out,
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output i2c_clk_out,
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output i2c_data_oe,
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output i2c_data_oe,
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output i2c_clk_oe,
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output i2c_clk_oe,
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input [(DW-1):0] wb_data_i,
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input [(DW-1):0] wb_data_i,
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output [(DW-1):0] wb_data_o,
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output [(DW-1):0] wb_data_o,
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output [(AW-1):0] wb_addr_o,
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output [(AW-1):0] wb_addr_o,
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output [3:0] wb_sel_o,
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output [3:0] wb_sel_o,
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output wb_we_o,
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output wb_we_o,
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output wb_cyc_o,
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output wb_cyc_o,
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output wb_stb_o,
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output wb_stb_o,
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input wb_ack_i,
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input wb_ack_i,
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input wb_err_i,
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input wb_err_i,
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input wb_rty_i,
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input wb_rty_i,
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input wb_clk_i,
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input wb_clk_i,
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input wb_rst_i
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input wb_rst_i
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// wires
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// wires
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wire tip_addr_byte;
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wire tip_addr_byte;
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wire tip_read_byte;
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wire tip_read_byte;
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wire tip_write_byte;
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wire tip_write_byte;
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wire tip_wr_ack;
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wire tip_wr_ack;
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wire tip_rd_ack;
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wire tip_rd_ack;
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wire tip_addr_ack;
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wire tip_addr_ack;
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// wire i2c_ack_out = 1'b0;
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// wire i2c_ack_out = 1'b0;
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wire i2c_ack_out;
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wire i2c_ack_out;
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wire i2c_ack_done;
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wire i2c_ack_done;
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wire [7:0] i2c_byte_out;
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wire [7:0] i2c_byte_out;
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wire i2c_parallel_load;
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wire i2c_parallel_load;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// glitch filter
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// glitch filter
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wire gf_i2c_data_in;
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wire gf_i2c_data_in;
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wire gf_i2c_data_in_rise;
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wire gf_i2c_data_in_rise;
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wire gf_i2c_data_in_fall;
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wire gf_i2c_data_in_fall;
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glitch_filter
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glitch_filter
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i_gf_i2c_data_in(
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i_gf_i2c_data_in(
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.in(i2c_data_in),
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.in(i2c_data_in),
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.out(gf_i2c_data_in),
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.out(gf_i2c_data_in),
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.rise(gf_i2c_data_in_rise),
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.rise(gf_i2c_data_in_rise),
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.fall(gf_i2c_data_in_fall),
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.fall(gf_i2c_data_in_fall),
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i)
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.rst(wb_rst_i)
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);
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);
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wire gf_i2c_clk_in;
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wire gf_i2c_clk_in;
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wire gf_i2c_clk_in_rise;
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wire gf_i2c_clk_in_rise;
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wire gf_i2c_clk_in_fall;
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wire gf_i2c_clk_in_fall;
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glitch_filter
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glitch_filter
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i_gf_i2c_clk_in(
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i_gf_i2c_clk_in(
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.in(i2c_clk_in),
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.in(i2c_clk_in),
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.out(gf_i2c_clk_in),
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.out(gf_i2c_clk_in),
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.rise(gf_i2c_clk_in_rise),
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.rise(gf_i2c_clk_in_rise),
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.fall(gf_i2c_clk_in_fall),
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.fall(gf_i2c_clk_in_fall),
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i)
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.rst(wb_rst_i)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// i2c data shift register w/ parallel load
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// i2c data shift register w/ parallel load
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reg [8:0] i2c_data_in_r; // add throw away bit for serial_out
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reg [8:0] i2c_data_in_r; // add throw away bit for serial_out
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wire serial_out = i2c_data_in_r[8];
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wire serial_out = i2c_data_in_r[8];
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if( i2c_parallel_load )
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if( i2c_parallel_load )
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i2c_data_in_r[7:0] <= i2c_byte_out;
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i2c_data_in_r[7:0] <= i2c_byte_out;
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else if( (tip_write_byte & gf_i2c_clk_in_rise) | (tip_read_byte & gf_i2c_clk_in_fall) )
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else if( (tip_write_byte & gf_i2c_clk_in_rise) | (tip_read_byte & gf_i2c_clk_in_fall) )
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i2c_data_in_r <= {i2c_data_in_r[7:0], gf_i2c_data_in};
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i2c_data_in_r <= {i2c_data_in_r[7:0], gf_i2c_data_in};
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// main state machine
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// main state machine
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i2c_to_wb_fsm
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i2c_to_wb_fsm
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i_i2c_to_wb_fsm
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i_i2c_to_wb_fsm
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(
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(
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.i2c_data(gf_i2c_data_in),
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.i2c_data(gf_i2c_data_in),
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.i2c_data_rise(gf_i2c_data_in_rise),
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.i2c_data_rise(gf_i2c_data_in_rise),
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.i2c_data_fall(gf_i2c_data_in_fall),
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.i2c_data_fall(gf_i2c_data_in_fall),
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.i2c_clk(gf_i2c_clk_in),
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.i2c_clk(gf_i2c_clk_in),
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.i2c_clk_rise(gf_i2c_clk_in_rise),
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.i2c_clk_rise(gf_i2c_clk_in_rise),
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.i2c_clk_fall(gf_i2c_clk_in_fall),
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.i2c_clk_fall(gf_i2c_clk_in_fall),
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.i2c_r_w_bit(i2c_data_in_r[0]),
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.i2c_r_w_bit(i2c_data_in_r[0]),
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.i2c_ack_out(i2c_ack_out),
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.i2c_ack_out(i2c_ack_out),
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.i2c_ack_done(i2c_ack_done),
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.i2c_ack_done(i2c_ack_done),
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.tip_addr_byte(tip_addr_byte),
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.tip_addr_byte(tip_addr_byte),
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.tip_read_byte(tip_read_byte),
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.tip_read_byte(tip_read_byte),
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.tip_write_byte(tip_write_byte),
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.tip_write_byte(tip_write_byte),
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.tip_wr_ack(tip_wr_ack),
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.tip_wr_ack(tip_wr_ack),
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.tip_rd_ack(tip_rd_ack),
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.tip_rd_ack(tip_rd_ack),
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.tip_addr_ack(tip_addr_ack),
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.tip_addr_ack(tip_addr_ack),
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.state_out(),
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.state_out(),
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.i2c_error(),
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.i2c_error(),
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i)
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.wb_rst_i(wb_rst_i)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// i2c_to_wb_config
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// i2c_to_wb_config
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i2c_to_wb_config
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i2c_to_wb_config
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i_i2c_to_wb_config
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i_i2c_to_wb_config
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(
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(
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.i2c_byte_in(i2c_data_in_r[7:0]),
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.i2c_byte_in(i2c_data_in_r[7:0]),
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.tip_addr_ack(tip_addr_ack),
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.tip_addr_ack(tip_addr_ack),
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.i2c_ack_out(i2c_ack_out),
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.i2c_ack_out(i2c_ack_out),
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i)
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.wb_rst_i(wb_rst_i)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// i2c_to_wb_if
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// i2c_to_wb_if
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i2c_to_wb_if #( .DW(DW), .AW(AW) )
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i2c_to_wb_if #( .DW(DW), .AW(AW) )
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i_i2c_to_wb_if(
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i_i2c_to_wb_if(
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.i2c_data(gf_i2c_data_in),
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.i2c_data(gf_i2c_data_in),
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.i2c_ack_done(i2c_ack_done),
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.i2c_ack_done(i2c_ack_done),
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.i2c_byte_in(i2c_data_in_r[7:0]),
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.i2c_byte_in(i2c_data_in_r[7:0]),
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.i2c_byte_out(i2c_byte_out),
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.i2c_byte_out(i2c_byte_out),
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.i2c_parallel_load(i2c_parallel_load),
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.i2c_parallel_load(i2c_parallel_load),
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.tip_wr_ack(tip_wr_ack),
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.tip_wr_ack(tip_wr_ack),
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.tip_rd_ack(tip_rd_ack),
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.tip_rd_ack(tip_rd_ack),
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.tip_addr_ack(tip_addr_ack),
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.tip_addr_ack(tip_addr_ack),
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.wb_data_i(wb_data_i),
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.wb_data_i(wb_data_i),
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.wb_data_o(wb_data_o),
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.wb_data_o(wb_data_o),
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.wb_addr_o(wb_addr_o),
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.wb_addr_o(wb_addr_o),
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.wb_sel_o(wb_sel_o),
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.wb_sel_o(wb_sel_o),
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.wb_we_o(wb_we_o),
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.wb_we_o(wb_we_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_stb_o(wb_stb_o),
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.wb_stb_o(wb_stb_o),
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.wb_ack_i(wb_ack_i),
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.wb_ack_i(wb_ack_i),
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.wb_err_i(wb_err_i),
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.wb_err_i(wb_err_i),
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.wb_rty_i(wb_rty_i),
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.wb_rty_i(wb_rty_i),
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i)
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.wb_rst_i(wb_rst_i)
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);
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);
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// i2c_data out sync
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// i2c_data out sync
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reg i2c_data_oe_r;
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reg i2c_data_oe_r;
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if( wb_rst_i )
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if( wb_rst_i )
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i2c_data_oe_r <= 1'b0;
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i2c_data_oe_r <= 1'b0;
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else if( gf_i2c_clk_in_fall )
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else if( gf_i2c_clk_in_fall )
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i2c_data_oe_r <= tip_read_byte | tip_wr_ack;
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i2c_data_oe_r <= tip_read_byte | tip_wr_ack;
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reg i2c_data_mux_select_r;
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reg i2c_data_mux_select_r;
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if( gf_i2c_clk_in_fall )
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if( gf_i2c_clk_in_fall )
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i2c_data_mux_select_r <= tip_wr_ack;
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i2c_data_mux_select_r <= tip_wr_ack;
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// outputs
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// outputs
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assign i2c_data_out = i2c_data_mux_select_r ? i2c_ack_out : serial_out;
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assign i2c_data_out = i2c_data_mux_select_r ? i2c_ack_out : serial_out;
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assign i2c_data_oe = i2c_data_oe_r;
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assign i2c_data_oe = i2c_data_oe_r;
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assign i2c_clk_out = 1'b1;
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assign i2c_clk_out = 1'b1;
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assign i2c_clk_oe = 1'b0;
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assign i2c_clk_oe = 1'b0;
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endmodule
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endmodule
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