// ---------------------------------- testcase0.v ----------------------------
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// ---------------------------------- testcase0.v ----------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "i2cSlave_define.v"
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`include "i2cSlave_define.v"
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`include "i2cSlaveTB_defines.v"
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`include "i2cSlaveTB_defines.v"
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module testCase0();
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module testCase0();
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reg ack;
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reg ack;
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reg [7:0] data;
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reg [7:0] data;
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reg [15:0] dataWord;
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reg [15:0] dataWord;
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reg [7:0] dataRead;
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reg [7:0] dataRead;
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reg [7:0] dataWrite;
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reg [7:0] dataWrite;
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integer i;
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integer i;
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integer j;
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integer j;
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initial
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initial
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begin
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begin
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$write("\n\n");
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$write("\n\n");
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testHarness.reset;
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testHarness.reset;
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#1000;
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#1000;
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// set i2c master clock scale reg PRER = (48MHz / (5 * 400KHz) ) - 1
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// set i2c master clock scale reg PRER = (48MHz / (5 * 400KHz) ) - 1
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$write("Testing register read/write\n");
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$write("Testing register read/write\n");
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testHarness.u_wb_master_model.wb_write(1, `PRER_LO_REG , 8'h17);
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testHarness.u_wb_master_model.wb_write(1, `PRER_LO_REG , 8'h17);
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testHarness.u_wb_master_model.wb_write(1, `PRER_HI_REG , 8'h00);
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testHarness.u_wb_master_model.wb_write(1, `PRER_HI_REG , 8'h00);
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testHarness.u_wb_master_model.wb_cmp(1, `PRER_LO_REG , 8'h17);
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testHarness.u_wb_master_model.wb_cmp(1, `PRER_LO_REG , 8'h17);
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// enable i2c master
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// enable i2c master
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testHarness.u_wb_master_model.wb_write(1, `CTR_REG , 8'h80);
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testHarness.u_wb_master_model.wb_write(1, `CTR_REG , 8'h80);
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multiByteReadWrite.write({`I2C_ADDRESS, 1'b0}, 8'h00, 32'h89abcdef, `SEND_STOP);
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multiByteReadWrite.write({`I2C_ADDRESS, 1'b0}, 8'h00, 32'h89abcdef, `SEND_STOP);
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multiByteReadWrite.read({`I2C_ADDRESS, 1'b0}, 8'h00, 32'h89abcdef, dataWord, `NULL);
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multiByteReadWrite.read({`I2C_ADDRESS, 1'b0}, 8'h00, 32'h89abcdef, dataWord, `NULL);
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multiByteReadWrite.read({`I2C_ADDRESS, 1'b0}, 8'h04, 32'h12345678, dataWord, `NULL);
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multiByteReadWrite.read({`I2C_ADDRESS, 1'b0}, 8'h04, 32'h12345678, dataWord, `NULL);
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$write("Finished all tests\n");
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$write("Finished all tests\n");
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$stop;
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$stop;
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end
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end
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endmodule
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endmodule
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