//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// wb_master_model.v ////
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//// wb_master_model.v ////
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//// ////
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//// ////
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//// This file is part of the SPI IP core project ////
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//// This file is part of the SPI IP core project ////
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//// http://www.opencores.org/projects/spi/ ////
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//// http://www.opencores.org/projects/spi/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Srot (simons@opencores.org) ////
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//// - Simon Srot (simons@opencores.org) ////
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//// ////
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//// ////
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//// Based on: ////
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//// Based on: ////
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//// - i2c/bench/verilog/wb_master_model.v ////
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//// - i2c/bench/verilog/wb_master_model.v ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
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module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
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parameter dwidth = 32;
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parameter dwidth = 32;
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parameter awidth = 32;
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parameter awidth = 32;
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input clk, rst;
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input clk, rst;
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output [awidth -1:0] adr;
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output [awidth -1:0] adr;
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input [dwidth -1:0] din;
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input [dwidth -1:0] din;
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output [dwidth -1:0] dout;
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output [dwidth -1:0] dout;
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output cyc, stb;
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output cyc, stb;
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output we;
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output we;
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output [dwidth/8 -1:0] sel;
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output [dwidth/8 -1:0] sel;
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input ack, err, rty;
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input ack, err, rty;
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// Internal signals
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// Internal signals
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reg [awidth -1:0] adr;
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reg [awidth -1:0] adr;
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reg [dwidth -1:0] dout;
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reg [dwidth -1:0] dout;
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reg cyc, stb;
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reg cyc, stb;
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reg we;
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reg we;
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reg [dwidth/8 -1:0] sel;
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reg [dwidth/8 -1:0] sel;
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reg [dwidth -1:0] q;
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reg [dwidth -1:0] q;
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// Memory Logic
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// Memory Logic
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initial
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initial
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begin
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begin
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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cyc = 1'b0;
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cyc = 1'b0;
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stb = 1'bx;
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stb = 1'bx;
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we = 1'hx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
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#1;
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#1;
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end
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end
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// Wishbone write cycle
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// Wishbone write cycle
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task wb_write;
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task wb_write;
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input delay;
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input delay;
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integer delay;
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integer delay;
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d;
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input [dwidth -1:0] d;
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begin
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begin
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// wait initial delay
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// wait initial delay
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repeat(delay) @(posedge clk);
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repeat(delay) @(posedge clk);
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// assert wishbone signal
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// assert wishbone signal
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#1;
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#1;
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adr = a;
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adr = a;
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dout = d;
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dout = d;
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cyc = 1'b1;
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cyc = 1'b1;
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stb = 1'b1;
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stb = 1'b1;
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we = 1'b1;
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we = 1'b1;
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sel = {dwidth/8{1'b1}};
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sel = {dwidth/8{1'b1}};
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@(posedge clk);
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@(posedge clk);
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// wait for acknowledge from slave
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// wait for acknowledge from slave
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while(~ack) @(posedge clk);
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while(~ack) @(posedge clk);
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// negate wishbone signals
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// negate wishbone signals
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#1;
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#1;
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cyc = 1'b0;
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cyc = 1'b0;
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stb = 1'bx;
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stb = 1'bx;
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
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end
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end
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endtask
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endtask
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// Wishbone read cycle
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// Wishbone read cycle
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task wb_read;
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task wb_read;
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input delay;
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input delay;
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integer delay;
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integer delay;
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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output [dwidth -1:0] d;
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output [dwidth -1:0] d;
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begin
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begin
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// wait initial delay
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// wait initial delay
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repeat(delay) @(posedge clk);
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repeat(delay) @(posedge clk);
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// assert wishbone signals
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// assert wishbone signals
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#1;
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#1;
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adr = a;
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adr = a;
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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cyc = 1'b1;
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cyc = 1'b1;
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stb = 1'b1;
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stb = 1'b1;
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we = 1'b0;
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we = 1'b0;
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sel = {dwidth/8{1'b1}};
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sel = {dwidth/8{1'b1}};
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@(posedge clk);
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@(posedge clk);
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// wait for acknowledge from slave
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// wait for acknowledge from slave
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while(~ack) @(posedge clk);
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while(~ack) @(posedge clk);
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// negate wishbone signals
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// negate wishbone signals
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#1;
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#1;
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cyc = 1'b0;
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cyc = 1'b0;
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stb = 1'bx;
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stb = 1'bx;
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
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d = din;
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d = din;
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end
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end
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endtask
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endtask
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// Wishbone compare cycle (read data from location and compare with expected data)
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// Wishbone compare cycle (read data from location and compare with expected data)
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task wb_cmp;
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task wb_cmp;
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input delay;
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input delay;
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integer delay;
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integer delay;
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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input [dwidth -1:0] d_exp;
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input [dwidth -1:0] d_exp;
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begin
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begin
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wb_read (delay, a, q);
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wb_read (delay, a, q);
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if (d_exp !== q)
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if (d_exp !== q)
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$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
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$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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