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---- ----
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---- ----
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---- WISHBONE I2S Interface IP Core ----
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---- WISHBONE I2S Interface IP Core ----
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---- ----
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---- ----
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---- This file is part of the I2S Interface project ----
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---- This file is part of the I2S Interface project ----
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---- http://www.opencores.org/cores/i2s_interface/ ----
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---- http://www.opencores.org/cores/i2s_interface/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- I2S receiver component declarations. ----
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---- I2S receiver component declarations. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- De-linting.
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-- De-linting.
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--
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--
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-- Revision 1.1 2004/08/04 14:28:54 gedra
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-- Revision 1.1 2004/08/04 14:28:54 gedra
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-- Receiver component declarations.
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-- Receiver component declarations.
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--
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--
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package rx_i2s_pack is
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package rx_i2s_pack is
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-- components used in the receiver
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-- components used in the receiver
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component gen_control_reg
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component gen_control_reg
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generic (DATA_WIDTH : integer;
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generic (DATA_WIDTH : integer;
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-- note that this vector is (0 to xx), reverse order
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-- note that this vector is (0 to xx), reverse order
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ACTIVE_BIT_MASK : std_logic_vector);
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ACTIVE_BIT_MASK : std_logic_vector);
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port (
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port (
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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ctrl_wr : in std_logic; -- control register write
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ctrl_wr : in std_logic; -- control register write
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ctrl_rd : in std_logic; -- control register read
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ctrl_rd : in std_logic; -- control register read
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ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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component gen_event_reg
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component gen_event_reg
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generic (DATA_WIDTH : integer);
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generic (DATA_WIDTH : integer);
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port (
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port (
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clk : in std_logic; -- clock
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clk : in std_logic; -- clock
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rst : in std_logic; -- reset
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rst : in std_logic; -- reset
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evt_wr : in std_logic; -- event register write
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evt_wr : in std_logic; -- event register write
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evt_rd : in std_logic; -- event register read
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evt_rd : in std_logic; -- event register read
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evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
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event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
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evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
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evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
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evt_en : in std_logic; -- irq enable
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evt_en : in std_logic; -- irq enable
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evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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evt_irq : out std_logic); -- interrupt request
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evt_irq : out std_logic); -- interrupt request
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end component;
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end component;
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component dpram
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component dpram
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generic (DATA_WIDTH : positive;
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generic (DATA_WIDTH : positive;
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RAM_WIDTH : positive);
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RAM_WIDTH : positive);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic; -- reset is optional, not used here
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rst : in std_logic; -- reset is optional, not used here
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din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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wr_en : in std_logic;
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wr_en : in std_logic;
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rd_en : in std_logic;
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rd_en : in std_logic;
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wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);
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wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);
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rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);
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dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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component i2s_version
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component i2s_version
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generic (DATA_WIDTH : integer;
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generic (DATA_WIDTH : integer;
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ADDR_WIDTH : integer;
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ADDR_WIDTH : integer;
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IS_MASTER : integer);
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IS_MASTER : integer);
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port (
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port (
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ver_rd : in std_logic; -- version register read
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ver_rd : in std_logic; -- version register read
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ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end component;
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end component;
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component rx_i2s_wbd
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component rx_i2s_wbd
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generic (DATA_WIDTH : integer;
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generic (DATA_WIDTH : integer;
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ADDR_WIDTH : integer);
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ADDR_WIDTH : integer);
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port (
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port (
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wb_clk_i : in std_logic; -- wishbone clock
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wb_clk_i : in std_logic; -- wishbone clock
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wb_rst_i : in std_logic; -- reset signal
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wb_rst_i : in std_logic; -- reset signal
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wb_sel_i : in std_logic; -- select input
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wb_sel_i : in std_logic; -- select input
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wb_stb_i : in std_logic; -- strobe input
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wb_stb_i : in std_logic; -- strobe input
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wb_we_i : in std_logic; -- write enable
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wb_we_i : in std_logic; -- write enable
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wb_cyc_i : in std_logic; -- cycle input
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wb_cyc_i : in std_logic; -- cycle input
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wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension
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wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension
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wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier
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wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier
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wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
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wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
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data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
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data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
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wb_ack_o : out std_logic; -- acknowledge
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wb_ack_o : out std_logic; -- acknowledge
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wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
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wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
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version_rd : out std_logic; -- Version register read
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version_rd : out std_logic; -- Version register read
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config_rd : out std_logic; -- Config register read
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config_rd : out std_logic; -- Config register read
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config_wr : out std_logic; -- Config register write
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config_wr : out std_logic; -- Config register write
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intmask_rd : out std_logic; -- Interrupt mask register read
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intmask_rd : out std_logic; -- Interrupt mask register read
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intmask_wr : out std_logic; -- Interrupt mask register write
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intmask_wr : out std_logic; -- Interrupt mask register write
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intstat_rd : out std_logic; -- Interrupt status register read
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intstat_rd : out std_logic; -- Interrupt status register read
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intstat_wr : out std_logic; -- Interrupt status register read
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intstat_wr : out std_logic; -- Interrupt status register read
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mem_rd : out std_logic; -- Sample memory write
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mem_rd : out std_logic; -- Sample memory write
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mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr.
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mem_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0)); -- memory addr.
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end component;
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end component;
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component i2s_codec
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component i2s_codec
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generic (DATA_WIDTH : integer;
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generic (DATA_WIDTH : integer;
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ADDR_WIDTH : integer;
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ADDR_WIDTH : integer;
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IS_MASTER : integer range 0 to 1;
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IS_MASTER : integer range 0 to 1;
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IS_RECEIVER : integer range 0 to 1);
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IS_RECEIVER : integer range 0 to 1);
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port (
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port (
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wb_clk_i : in std_logic; -- wishbone clock
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wb_clk_i : in std_logic; -- wishbone clock
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conf_res : in std_logic_vector(5 downto 0); -- sample resolution
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conf_res : in std_logic_vector(5 downto 0); -- sample resolution
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conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio
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conf_ratio : in std_logic_vector(7 downto 0); -- clock divider ratio
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conf_swap : in std_logic; -- left/right sample order
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conf_swap : in std_logic; -- left/right sample order
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conf_en : in std_logic; -- transmitter/recevier enable
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conf_en : in std_logic; -- transmitter/recevier enable
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i2s_sd_i : in std_logic; -- I2S serial data input
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i2s_sd_i : in std_logic; -- I2S serial data input
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i2s_sck_i : in std_logic; -- I2S clock input
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i2s_sck_i : in std_logic; -- I2S clock input
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i2s_ws_i : in std_logic; -- I2S word select input
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i2s_ws_i : in std_logic; -- I2S word select input
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sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_dat_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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mem_rdwr : out std_logic; -- sample buffer read/write
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mem_rdwr : out std_logic; -- sample buffer read/write
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sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address
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sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address
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evt_hsbf : out std_logic; -- higher sample buf empty event
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evt_hsbf : out std_logic; -- higher sample buf empty event
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evt_lsbf : out std_logic; -- lower sample buf empty event
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evt_lsbf : out std_logic; -- lower sample buf empty event
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i2s_sd_o : out std_logic; -- I2S serial data output
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i2s_sd_o : out std_logic; -- I2S serial data output
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i2s_sck_o : out std_logic; -- I2S clock output
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i2s_sck_o : out std_logic; -- I2S clock output
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i2s_ws_o : out std_logic); -- I2S word select output
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i2s_ws_o : out std_logic); -- I2S word select output
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end component;
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end component;
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end rx_i2s_pack;
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end rx_i2s_pack;
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