----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- WISHBONE I2S Interface IP Core ----
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---- WISHBONE I2S Interface IP Core ----
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---- ----
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---- ----
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---- This file is part of the I2S Interface project ----
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---- This file is part of the I2S Interface project ----
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---- http://www.opencores.org/cores/i2s_interface/ ----
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---- http://www.opencores.org/cores/i2s_interface/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- I2S receiver. Top level entity for the receiver core, ----
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---- I2S receiver. Top level entity for the receiver core, ----
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---- master mode. ----
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---- master mode. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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--
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--
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-- CVS Revision History
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-- CVS Revision History
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- Revision 1.2 2004/08/06 18:55:43 gedra
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-- De-linting.
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-- De-linting.
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--
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--
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-- Revision 1.1 2004/08/04 14:29:34 gedra
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-- Revision 1.1 2004/08/04 14:29:34 gedra
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-- Receiver top level, master mode.
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-- Receiver top level, master mode.
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--
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--
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--
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--
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.rx_i2s_pack.all;
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use work.rx_i2s_pack.all;
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entity rx_i2s_topm is
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entity rx_i2s_topm is
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generic (DATA_WIDTH : integer range 16 to 32;
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generic (DATA_WIDTH : integer range 16 to 32;
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ADDR_WIDTH : integer range 5 to 32);
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ADDR_WIDTH : integer range 5 to 32);
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port (
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port (
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wb_clk_i : in std_logic;
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wb_clk_i : in std_logic;
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wb_rst_i : in std_logic;
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wb_rst_i : in std_logic;
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wb_sel_i : in std_logic;
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wb_sel_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_we_i : in std_logic;
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wb_we_i : in std_logic;
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wb_cyc_i : in std_logic;
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wb_cyc_i : in std_logic;
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wb_bte_i : in std_logic_vector(1 downto 0);
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wb_bte_i : in std_logic_vector(1 downto 0);
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wb_cti_i : in std_logic_vector(2 downto 0);
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wb_cti_i : in std_logic_vector(2 downto 0);
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wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0);
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wb_dat_i : in std_logic_vector(DATA_WIDTH -1 downto 0);
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i2s_sd_i : in std_logic; -- I2S data input
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i2s_sd_i : in std_logic; -- I2S data input
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wb_ack_o : out std_logic;
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wb_ack_o : out std_logic;
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wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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rx_int_o : out std_logic; -- Interrupt line
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rx_int_o : out std_logic; -- Interrupt line
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i2s_sck_o : out std_logic; -- I2S clock out
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i2s_sck_o : out std_logic; -- I2S clock out
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i2s_ws_o : out std_logic); -- I2S word select out
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i2s_ws_o : out std_logic); -- I2S word select out
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end rx_i2s_topm;
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end rx_i2s_topm;
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architecture rtl of rx_i2s_topm is
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architecture rtl of rx_i2s_topm is
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signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal data_out, version_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal version_rd : std_logic;
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signal version_rd : std_logic;
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signal config_rd, config_wr, status_rd : std_logic;
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signal config_rd, config_wr, status_rd : std_logic;
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signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal config_dout, status_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal config_bits : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intmask_bits, intmask_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intmask_rd, intmask_wr : std_logic;
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signal intmask_rd, intmask_wr : std_logic;
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signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intstat_events : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intstat_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal intstat_rd, intstat_wr : std_logic;
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signal intstat_rd, intstat_wr : std_logic;
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signal evt_hsbf, evt_lsbf : std_logic;
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signal evt_hsbf, evt_lsbf : std_logic;
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signal mem_wr, mem_rd : std_logic;
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signal mem_wr, mem_rd : std_logic;
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signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
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signal sbuf_rd_adr, sbuf_wr_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
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signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal sbuf_dout, sbuf_din, zeros : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal conf_res : std_logic_vector(5 downto 0);
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signal conf_res : std_logic_vector(5 downto 0);
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signal conf_ratio : std_logic_vector(7 downto 0);
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signal conf_ratio : std_logic_vector(7 downto 0);
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signal conf_rswap, conf_rinten, conf_rxen : std_logic;
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signal conf_rswap, conf_rinten, conf_rxen : std_logic;
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signal zero : std_logic;
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signal zero : std_logic;
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begin
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begin
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-- Data bus or'ing
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-- Data bus or'ing
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data_out <= version_dout or config_dout or intmask_dout or intstat_dout
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data_out <= version_dout or config_dout or intmask_dout or intstat_dout
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when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout;
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when wb_adr_i(ADDR_WIDTH - 1) = '0' else sbuf_dout;
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-- Wishbone bus cycle decoder
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-- Wishbone bus cycle decoder
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WB : rx_i2s_wbd
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WB : rx_i2s_wbd
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generic map (
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generic map (
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DATA_WIDTH => DATA_WIDTH,
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DATA_WIDTH => DATA_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH)
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ADDR_WIDTH => ADDR_WIDTH)
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port map (
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port map (
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wb_clk_i => wb_clk_i,
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wb_clk_i => wb_clk_i,
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wb_rst_i => wb_rst_i,
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wb_rst_i => wb_rst_i,
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wb_sel_i => wb_sel_i,
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wb_sel_i => wb_sel_i,
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wb_stb_i => wb_stb_i,
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wb_stb_i => wb_stb_i,
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wb_we_i => wb_we_i,
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wb_we_i => wb_we_i,
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wb_cyc_i => wb_cyc_i,
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wb_cyc_i => wb_cyc_i,
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wb_bte_i => wb_bte_i,
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wb_bte_i => wb_bte_i,
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wb_cti_i => wb_cti_i,
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wb_cti_i => wb_cti_i,
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wb_adr_i => wb_adr_i,
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wb_adr_i => wb_adr_i,
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data_out => data_out,
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data_out => data_out,
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wb_ack_o => wb_ack_o,
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wb_ack_o => wb_ack_o,
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wb_dat_o => wb_dat_o,
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wb_dat_o => wb_dat_o,
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version_rd => version_rd,
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version_rd => version_rd,
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config_rd => config_rd,
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config_rd => config_rd,
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config_wr => config_wr,
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config_wr => config_wr,
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intmask_rd => intmask_rd,
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intmask_rd => intmask_rd,
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intmask_wr => intmask_wr,
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intmask_wr => intmask_wr,
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intstat_rd => intstat_rd,
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intstat_rd => intstat_rd,
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intstat_wr => intstat_wr,
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intstat_wr => intstat_wr,
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mem_rd => mem_rd,
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mem_rd => mem_rd,
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mem_addr => sbuf_rd_adr);
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mem_addr => sbuf_rd_adr);
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-- TxVersion - Version register
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-- TxVersion - Version register
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VER : i2s_version
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VER : i2s_version
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generic map (
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generic map (
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DATA_WIDTH => DATA_WIDTH,
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DATA_WIDTH => DATA_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH,
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IS_MASTER => 1)
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IS_MASTER => 1)
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port map (
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port map (
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ver_rd => version_rd,
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ver_rd => version_rd,
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ver_dout => version_dout);
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ver_dout => version_dout);
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-- TxConfig - Configuration register
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-- TxConfig - Configuration register
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CG32 : if DATA_WIDTH = 32 generate
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CG32 : if DATA_WIDTH = 32 generate
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CONF : gen_control_reg
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CONF : gen_control_reg
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generic map (
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generic map (
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DATA_WIDTH => 32,
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DATA_WIDTH => 32,
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ACTIVE_BIT_MASK => "11100000111111111111110000000000")
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ACTIVE_BIT_MASK => "11100000111111111111110000000000")
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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ctrl_wr => config_wr,
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ctrl_wr => config_wr,
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ctrl_rd => config_rd,
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ctrl_rd => config_rd,
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ctrl_din => wb_dat_i,
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ctrl_din => wb_dat_i,
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ctrl_dout => config_dout,
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ctrl_dout => config_dout,
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ctrl_bits => config_bits);
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ctrl_bits => config_bits);
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conf_res(5 downto 0) <= config_bits(21 downto 16);
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conf_res(5 downto 0) <= config_bits(21 downto 16);
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end generate CG32;
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end generate CG32;
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CG16 : if DATA_WIDTH = 16 generate
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CG16 : if DATA_WIDTH = 16 generate
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CONF : gen_control_reg
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CONF : gen_control_reg
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generic map (
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generic map (
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DATA_WIDTH => 16,
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DATA_WIDTH => 16,
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ACTIVE_BIT_MASK => "1110000011111111")
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ACTIVE_BIT_MASK => "1110000011111111")
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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ctrl_wr => config_wr,
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ctrl_wr => config_wr,
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ctrl_rd => config_rd,
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ctrl_rd => config_rd,
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ctrl_din => wb_dat_i,
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ctrl_din => wb_dat_i,
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ctrl_dout => config_dout,
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ctrl_dout => config_dout,
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ctrl_bits => config_bits);
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ctrl_bits => config_bits);
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conf_res(5 downto 0) <= "010000"; -- 16bit only
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conf_res(5 downto 0) <= "010000"; -- 16bit only
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end generate CG16;
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end generate CG16;
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conf_ratio(7 downto 0) <= config_bits(15 downto 8);
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conf_ratio(7 downto 0) <= config_bits(15 downto 8);
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conf_rswap <= config_bits(2);
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conf_rswap <= config_bits(2);
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conf_rinten <= config_bits(1);
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conf_rinten <= config_bits(1);
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conf_rxen <= config_bits(0);
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conf_rxen <= config_bits(0);
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-- TxIntMask - interrupt mask register
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-- TxIntMask - interrupt mask register
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IM32 : if DATA_WIDTH = 32 generate
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IM32 : if DATA_WIDTH = 32 generate
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IMASK : gen_control_reg
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IMASK : gen_control_reg
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generic map (
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generic map (
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DATA_WIDTH => 32,
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DATA_WIDTH => 32,
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ACTIVE_BIT_MASK => "11000000000000000000000000000000")
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ACTIVE_BIT_MASK => "11000000000000000000000000000000")
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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ctrl_wr => intmask_wr,
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ctrl_wr => intmask_wr,
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ctrl_rd => intmask_rd,
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ctrl_rd => intmask_rd,
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ctrl_din => wb_dat_i,
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ctrl_din => wb_dat_i,
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ctrl_dout => intmask_dout,
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ctrl_dout => intmask_dout,
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ctrl_bits => intmask_bits);
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ctrl_bits => intmask_bits);
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end generate IM32;
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end generate IM32;
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IM16 : if DATA_WIDTH = 16 generate
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IM16 : if DATA_WIDTH = 16 generate
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IMASK : gen_control_reg
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IMASK : gen_control_reg
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generic map (
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generic map (
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DATA_WIDTH => 16,
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DATA_WIDTH => 16,
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ACTIVE_BIT_MASK => "1100000000000000")
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ACTIVE_BIT_MASK => "1100000000000000")
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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ctrl_wr => intmask_wr,
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ctrl_wr => intmask_wr,
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ctrl_rd => intmask_rd,
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ctrl_rd => intmask_rd,
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ctrl_din => wb_dat_i,
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ctrl_din => wb_dat_i,
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ctrl_dout => intmask_dout,
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ctrl_dout => intmask_dout,
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ctrl_bits => intmask_bits);
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ctrl_bits => intmask_bits);
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end generate IM16;
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end generate IM16;
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-- TxIntStat - interrupt status register
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-- TxIntStat - interrupt status register
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ISTAT : gen_event_reg
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ISTAT : gen_event_reg
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generic map (
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generic map (
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DATA_WIDTH => DATA_WIDTH)
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DATA_WIDTH => DATA_WIDTH)
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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evt_wr => intstat_wr,
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evt_wr => intstat_wr,
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evt_rd => intstat_rd,
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evt_rd => intstat_rd,
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evt_din => wb_dat_i,
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evt_din => wb_dat_i,
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evt_dout => intstat_dout,
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evt_dout => intstat_dout,
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event => intstat_events,
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event => intstat_events,
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evt_mask => intmask_bits,
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evt_mask => intmask_bits,
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evt_en => conf_rinten,
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evt_en => conf_rinten,
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evt_irq => rx_int_o);
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evt_irq => rx_int_o);
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intstat_events(0) <= evt_lsbf; -- lower sample buffer empty
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intstat_events(0) <= evt_lsbf; -- lower sample buffer empty
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intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty
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intstat_events(1) <= evt_hsbf; -- higher sampel buffer empty
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intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0');
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intstat_events(DATA_WIDTH - 1 downto 2) <= (others => '0');
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|
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-- Sample buffer memory
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-- Sample buffer memory
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MEM : dpram
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MEM : dpram
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generic map (
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generic map (
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DATA_WIDTH => DATA_WIDTH,
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DATA_WIDTH => DATA_WIDTH,
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RAM_WIDTH => ADDR_WIDTH - 1)
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RAM_WIDTH => ADDR_WIDTH - 1)
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port map (
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port map (
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clk => wb_clk_i,
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clk => wb_clk_i,
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rst => wb_rst_i,
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rst => wb_rst_i,
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din => sbuf_din,
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din => sbuf_din,
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wr_en => mem_wr,
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wr_en => mem_wr,
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rd_en => mem_rd,
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rd_en => mem_rd,
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wr_addr => sbuf_wr_adr,
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wr_addr => sbuf_wr_adr,
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rd_addr => sbuf_rd_adr,
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rd_addr => sbuf_rd_adr,
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dout => sbuf_dout);
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dout => sbuf_dout);
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|
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-- Receive decoder
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-- Receive decoder
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zero <= '0';
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zero <= '0';
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zeros <= (others => '0');
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zeros <= (others => '0');
|
|
|
DEC : i2s_codec
|
DEC : i2s_codec
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generic map (DATA_WIDTH => DATA_WIDTH,
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generic map (DATA_WIDTH => DATA_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH,
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ADDR_WIDTH => ADDR_WIDTH,
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IS_MASTER => 1,
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IS_MASTER => 1,
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IS_RECEIVER => 1)
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IS_RECEIVER => 1)
|
port map (
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port map (
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wb_clk_i => wb_clk_i,
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wb_clk_i => wb_clk_i,
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conf_res => conf_res,
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conf_res => conf_res,
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conf_ratio => conf_ratio,
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conf_ratio => conf_ratio,
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conf_swap => conf_rswap,
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conf_swap => conf_rswap,
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conf_en => conf_rxen,
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conf_en => conf_rxen,
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i2s_sd_i => i2s_sd_i,
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i2s_sd_i => i2s_sd_i,
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i2s_sck_i => zero,
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i2s_sck_i => zero,
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i2s_ws_i => zero,
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i2s_ws_i => zero,
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sample_dat_i => zeros,
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sample_dat_i => zeros,
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sample_dat_o => sbuf_din,
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sample_dat_o => sbuf_din,
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mem_rdwr => mem_wr,
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mem_rdwr => mem_wr,
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sample_addr => sbuf_wr_adr,
|
sample_addr => sbuf_wr_adr,
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evt_hsbf => evt_hsbf,
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evt_hsbf => evt_hsbf,
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evt_lsbf => evt_lsbf,
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evt_lsbf => evt_lsbf,
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i2s_sd_o => open,
|
i2s_sd_o => open,
|
i2s_sck_o => i2s_sck_o,
|
i2s_sck_o => i2s_sck_o,
|
i2s_ws_o => i2s_ws_o);
|
i2s_ws_o => i2s_ws_o);
|
|
|
end rtl;
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end rtl;
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