`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// IBM 650 Reconstruction in Verilog (i650)
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//
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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// http:////www.opencores.org/project,i650
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//
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//
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// Description: Register validity checking.
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// Description: Register validity checking.
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//
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//
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// Additional Comments: See US 2959351, Fig. 82.
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// Additional Comments: See US 2959351, Fig. 82.
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//
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//
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// Copyright (c) 2015 Robert Abeles
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// Copyright (c) 2015 Robert Abeles
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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`include "defines.v"
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module biq_check (
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module biq_check (
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input [0:6] biq,
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input [0:6] biq,
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output invalid
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output invalid
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);
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);
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// .
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// Validate bi-quinary digit.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire q0_or_q1 = biq[`biq_q0] | biq[`biq_q1];
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wire q0_or_q1 = biq[`biq_q0] | biq[`biq_q1];
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wire q2_or_q3_or_q4 = biq[`biq_q2] | biq[`biq_q3] | biq[`biq_q4];
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wire q2_or_q3_or_q4 = biq[`biq_q2] | biq[`biq_q3] | biq[`biq_q4];
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wire b0_or_b5 = biq[`biq_b0] | biq[`biq_b5];
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wire b0_or_b5 = biq[`biq_b0] | biq[`biq_b5];
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wire q0_and_q1 = biq[`biq_q0] & biq[`biq_q1];
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wire q0_and_q1 = biq[`biq_q0] & biq[`biq_q1];
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wire b0_and_b5 = biq[`biq_b0] & biq[`biq_b5];
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wire b0_and_b5 = biq[`biq_b0] & biq[`biq_b5];
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wire q2_and_q4 = biq[`biq_q2] & biq[`biq_q4];
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wire q2_and_q4 = biq[`biq_q2] & biq[`biq_q4];
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wire q3_and_q4 = biq[`biq_q3] & biq[`biq_q4];
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wire q3_and_q4 = biq[`biq_q3] & biq[`biq_q4];
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wire q2_and_q3 = biq[`biq_q2] & biq[`biq_q3];
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wire q2_and_q3 = biq[`biq_q2] & biq[`biq_q3];
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assign invalid = (q2_and_q4)
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assign invalid = (q2_and_q4)
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| (q3_and_q4)
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| (q3_and_q4)
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| (q2_and_q3)
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| (q2_and_q3)
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| (q0_or_q1 & q2_or_q3_or_q4)
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| (q0_or_q1 & q2_or_q3_or_q4)
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| (q0_and_q1)
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| (q0_and_q1)
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| (b0_and_b5)
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| (b0_and_b5)
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| ~(b0_or_b5 & (q0_or_q1 | q2_or_q3_or_q4));
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| ~(b0_or_b5 & (q0_or_q1 | q2_or_q3_or_q4));
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endmodule
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endmodule
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module checking (
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module checking (
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input rst,
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input rst,
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input bp,
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input bp,
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input d1_dx,
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input d1_dx,
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input [0:6] acc_ontime, prog_ontime, dist_ontime,
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input [0:6] acc_ontime, prog_ontime, dist_ontime,
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input error_reset, tlu_or_zero_check,
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input error_reset, tlu_or_zero_check,
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|
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output error_stop, acc_check_light, prog_check_light, dist_check_light
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output error_stop, acc_check_light, prog_check_light, dist_check_light
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);
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);
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reg acc_error, prog_error, dist_error;
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reg acc_error, prog_error, dist_error;
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wire acc_invalid, prog_invalid, dist_invalid;
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wire acc_invalid, prog_invalid, dist_invalid;
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biq_check bc1 (acc_ontime, acc_invalid);
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biq_check bc1 (acc_ontime, acc_invalid);
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biq_check bc2 (prog_ontime, prog_invalid);
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biq_check bc2 (prog_ontime, prog_invalid);
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biq_check bc3 (dist_ontime, dist_invalid);
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biq_check bc3 (dist_ontime, dist_invalid);
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assign error_stop = tlu_or_zero_check | acc_error | prog_error | dist_error;
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assign error_stop = tlu_or_zero_check | acc_error | prog_error | dist_error;
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assign acc_check_light = acc_error;
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assign prog_check_light = prog_error;
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assign dist_check_light = dist_error;
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always @(posedge bp)
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always @(posedge bp)
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if (rst) begin
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if (rst) begin
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acc_error <= 0;
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acc_error <= 0;
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prog_error <= 0;
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prog_error <= 0;
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dist_error <= 0;
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dist_error <= 0;
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end else if (error_reset) begin
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end else if (error_reset) begin
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acc_error <= 0;
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acc_error <= 0;
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prog_error <= 0;
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prog_error <= 0;
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dist_error <= 0;
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dist_error <= 0;
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end else begin
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end else begin
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if (acc_invalid) acc_error <= 1;
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if (acc_invalid) acc_error <= 1;
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if (prog_invalid & d1_dx) prog_error <= 1;
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if (prog_invalid & d1_dx) prog_error <= 1;
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if (dist_invalid) dist_error <= 1;
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if (dist_invalid) dist_error <= 1;
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end;
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end;
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endmodule
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endmodule
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