//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// IBM 650 Reconstruction in Verilog (i650)
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//
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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// http:////www.opencores.org/project,i650
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//
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//
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// Description: Global definitions.
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// Description: Global definitions.
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//
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//
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// Additional Comments:
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// Additional Comments:
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//
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//
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// Copyright (c) 2015 Robert Abeles
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// Copyright (c) 2015 Robert Abeles
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Bi-quinary binary codes
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// Bi-quinary binary codes
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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`define biq_blank 7'b00_00000
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`define biq_blank 7'b00_00000
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`define biq_0 7'b01_00001
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`define biq_0 7'b01_00001
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`define biq_1 7'b01_00010
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`define biq_1 7'b01_00010
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`define biq_2 7'b01_00100
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`define biq_2 7'b01_00100
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`define biq_3 7'b01_01000
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`define biq_3 7'b01_01000
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`define biq_4 7'b01_10000
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`define biq_4 7'b01_10000
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`define biq_5 7'b10_00001
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`define biq_5 7'b10_00001
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`define biq_6 7'b10_00010
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`define biq_6 7'b10_00010
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`define biq_7 7'b10_00100
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`define biq_7 7'b10_00100
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`define biq_8 7'b10_01000
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`define biq_8 7'b10_01000
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`define biq_9 7'b10_10000
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`define biq_9 7'b10_10000
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`define biq_plus 7'b10_10000
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`define biq_plus 7'b10_10000
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`define biq_minus 7'b10_01000
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`define biq_minus 7'b10_01000
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Bi-quinary bit numbers
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// Bi-quinary bit numbers
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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`define biq_b5 0
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`define biq_b5 0
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`define biq_b0 1
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`define biq_b0 1
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`define biq_q4 2
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`define biq_q4 2
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`define biq_q3 3
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`define biq_q3 3
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`define biq_q2 4
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`define biq_q2 4
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`define biq_q1 5
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`define biq_q1 5
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`define biq_q0 6
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`define biq_q0 6
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// 2 of 5 drum recording codes
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// 2 of 5 drum recording codes
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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`define drum2of5_blank 5'b00000
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`define drum2of5_blank 5'b00000
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`define drum2of5_0 5'b01100
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`define drum2of5_0 5'b01100
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`define drum2of5_1 5'b11000
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`define drum2of5_1 5'b11000
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`define drum2of5_2 5'b10100
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`define drum2of5_2 5'b10100
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`define drum2of5_3 5'b10010
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`define drum2of5_3 5'b10010
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`define drum2of5_4 5'b01010
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`define drum2of5_4 5'b01010
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`define drum2of5_5 5'b00110
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`define drum2of5_5 5'b00110
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`define drum2of5_6 5'b10001
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`define drum2of5_6 5'b10001
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`define drum2of5_7 5'b01001
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`define drum2of5_7 5'b01001
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`define drum2of5_8 5'b00101
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`define drum2of5_8 5'b00101
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`define drum2of5_9 5'b00011
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`define drum2of5_9 5'b00011
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Console control commands
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// Console control commands
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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`define cmd_none 6'd0
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`define cmd_none 6'd0
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// set switch position
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// set switch position
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`define cmd_pgm_sw_stop 6'd1
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`define cmd_pgm_sw_stop 6'd1
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`define cmd_pgm_sw_run 6'd2
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`define cmd_pgm_sw_run 6'd2
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`define cmd_half_cycle_sw_run 6'd3
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`define cmd_half_cycle_sw_run 6'd3
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`define cmd_half_cycle_sw_half 6'd4
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`define cmd_half_cycle_sw_half 6'd4
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`define cmd_ctl_sw_addr_stop 6'd5
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`define cmd_ctl_sw_addr_stop 6'd5
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`define cmd_ctl_sw_run 6'd6
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`define cmd_ctl_sw_run 6'd6
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`define cmd_ctl_sw_manual 6'd7
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`define cmd_ctl_sw_manual 6'd7
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`define cmd_disp_sw_lacc 6'd8
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`define cmd_disp_sw_lacc 6'd8
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`define cmd_disp_sw_uacc 6'd9
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`define cmd_disp_sw_uacc 6'd9
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`define cmd_disp_sw_dist 6'd10
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`define cmd_disp_sw_dist 6'd10
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`define cmd_disp_sw_prog 6'd11
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`define cmd_disp_sw_prog 6'd11
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`define cmd_disp_sw_ri 6'd12
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`define cmd_disp_sw_ri 6'd12
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`define cmd_disp_sw_ro 6'd13
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`define cmd_disp_sw_ro 6'd13
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`define cmd_ovflw_sw_stop 6'd14
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`define cmd_ovflw_sw_stop 6'd14
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`define cmd_ovflw_sw_sense 6'd15
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`define cmd_ovflw_sw_sense 6'd15
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`define cmd_err_sw_stop 6'd16
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`define cmd_err_sw_stop 6'd16
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`define cmd_err_sw_sense 6'd17
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`define cmd_err_sw_sense 6'd17
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// press key
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// press key
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`define cmd_xfer_key 6'd18
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`define cmd_xfer_key 6'd18
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`define cmd_pgm_start_key 6'd19
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`define cmd_pgm_start_key 6'd19
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`define cmd_pgm_stop_key 6'd20
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`define cmd_pgm_stop_key 6'd20
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`define cmd_pgm_reset_key 6'd21
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`define cmd_pgm_reset_key 6'd21
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`define cmd_comp_reset_key 6'd22
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`define cmd_comp_reset_key 6'd22
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`define cmd_acc_reset_key 6'd23
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`define cmd_acc_reset_key 6'd23
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`define cmd_err_reset_key 6'd24
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`define cmd_err_reset_key 6'd24
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`define cmd_err_sense_reset_key 6'd25
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`define cmd_err_sense_reset_key 6'd25
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// set address select and storage entry switches
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// set address select and storage entry switches
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`define cmd_storage_entry_sw 6'd26
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`define cmd_storage_entry_sw 6'd26
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`define cmd_addr_sel_sw 6'd27
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`define cmd_addr_sel_sw 6'd27
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// read/write general storage
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// read/write general storage
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`define cmd_read_gs 6'd28
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`define cmd_read_gs 6'd28
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`define cmd_write_gs 6'd29
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`define cmd_write_gs 6'd29
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// read machine registers
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// read machine registers
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`define cmd_read_acc 6'd30
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`define cmd_read_acc 6'd30
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`define cmd_read_dist 6'd31
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`define cmd_read_dist 6'd31
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`define cmd_read_prog 6'd32
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`define cmd_read_prog 6'd32
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// general storage (drum)
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// general storage (drum)
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`define cmd_clear_gs 6'd33
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`define cmd_clear_gs 6'd33
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`define cmd_load_gs 6'd34
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`define cmd_load_gs 6'd34
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`define cmd_dump_gs 6'd35
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`define cmd_dump_gs 6'd35
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// resets
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// resets
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`define cmd_power_on_reset 6'd36
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`define cmd_power_on_reset 6'd36
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`define cmd_reset_console 6'd37
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`define cmd_reset_console 6'd37
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No newline at end of file
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No newline at end of file
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`define cmd_hard_reset 6'd38
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No newline at end of file
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No newline at end of file
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