`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// IBM 650 Reconstruction in Verilog (i650)
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//
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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// http:////www.opencores.org/project,i650
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//
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//
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// Description: 650 Timing.
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// Description: 650 Timing.
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//
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//
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// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
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// Additional Comments: See US 2959351, Fig. 53, 54 and 55. Additional index
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// counters provided to address general storage and register RAMs.
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// counters provided to address general storage and register RAMs.
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//
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//
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// Copyright (c) 2015 Robert Abeles
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// Copyright (c) 2015 Robert Abeles
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module timing (
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module timing (
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input clk,
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input clk,
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input rst,
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input rst,
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output reg ap, bp, cp, dp,
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output reg ap, bp, cp, dp,
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output reg dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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output reg dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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output reg d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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output reg d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
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//output reg dxcu_d1cu, d10cl_d0cu,
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//output reg dxcu_d1cu, d10cl_d0cu,
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output dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u,
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output dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u,
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output reg w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
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output reg w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
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output reg wl, wu, ewl,
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output reg wl, wu, ewl,
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output reg s0, s1, s2, s3, s4,
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output reg s0, s1, s2, s3, s4,
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output reg hp,
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output reg hp,
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|
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output reg[0:9] digit_idx,
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output reg[0:9] digit_idx,
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output reg[0:3] early_idx, ontime_idx
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output reg[0:3] early_idx, ontime_idx
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);
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);
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reg[0:3] digit_ctr;
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reg[0:3] digit_ctr;
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reg[0:3] word_ctr;
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reg[0:3] word_ctr;
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reg[0:2] sector_ctr;
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reg[0:2] sector_ctr;
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assign dxl = dx & wl;
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assign dxl = dx & wl;
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assign dxu = dx & wu;
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assign dxu = dx & wu;
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assign d0l = d0 & wl;
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assign d0l = d0 & wl;
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assign d0u = d0 & wu;
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assign d0u = d0 & wu;
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assign d1l = d1 & wl;
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assign d1l = d1 & wl;
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assign d1u = d1 & wu;
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assign d1u = d1 & wu;
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assign d2l = d2 & wl;
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assign d2l = d2 & wl;
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assign d10u = d10 & wu;
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assign d10u = d10 & wu;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// 650 four-phase clock
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// 650 four-phase clock
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge clk) begin
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always @(posedge rst, posedge clk) begin
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if (rst) begin
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if (rst) begin
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ap <= 1;
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ap <= 1;
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bp <= 0;
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bp <= 0;
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cp <= 0;
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cp <= 0;
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dp <= 0;
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dp <= 0;
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end else begin
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end else begin
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ap <= dp;
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ap <= dp;
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bp <= ap;
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bp <= ap;
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cp <= bp;
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cp <= bp;
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dp <= cp;
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dp <= cp;
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end;
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end;
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end;
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end;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Counter-based timing signals
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// Counter-based timing signals
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge dp) begin
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always @(posedge rst, posedge dp) begin
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if (rst) begin
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if (rst) begin
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dx <= 0;
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dx <= 0;
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d0 <= 0;
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d0 <= 0;
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d1 <= 0;
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d1 <= 0;
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d2 <= 0;
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d2 <= 0;
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d3 <= 0;
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d3 <= 0;
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d4 <= 0;
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d4 <= 0;
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d5 <= 0;
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d5 <= 0;
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d6 <= 0;
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d6 <= 0;
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d7 <= 0;
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d7 <= 0;
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d8 <= 0;
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d8 <= 0;
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d9 <= 0;
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d9 <= 0;
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d10 <= 0;
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d10 <= 0;
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d1_d5 <= 0;
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d1_d5 <= 0;
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d5_dx <= 0;
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d5_dx <= 0;
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d5_d10 <= 0;
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d5_d10 <= 0;
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d1_dx <= 0;
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d1_dx <= 0;
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d5_d9 <= 0;
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d5_d9 <= 0;
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d10_d1_d5 <= 0;
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d10_d1_d5 <= 0;
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w0 <= 0;
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w0 <= 0;
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w1 <= 0;
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w1 <= 0;
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w2 <= 0;
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w2 <= 0;
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w3 <= 0;
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w3 <= 0;
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w4 <= 0;
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w4 <= 0;
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w5 <= 0;
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w5 <= 0;
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w6 <= 0;
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w6 <= 0;
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w7 <= 0;
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w7 <= 0;
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w8 <= 0;
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w8 <= 0;
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w9 <= 0;
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w9 <= 0;
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wu <= 0;
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wu <= 0;
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wl <= 0;
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wl <= 0;
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ewl <= 0;
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ewl <= 0;
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s0 <= 0;
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s0 <= 0;
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s1 <= 0;
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s1 <= 0;
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s2 <= 0;
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s2 <= 0;
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s3 <= 0;
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s3 <= 0;
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s4 <= 0;
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s4 <= 0;
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hp <= 0;
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hp <= 0;
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digit_ctr <= 4'd0;
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digit_ctr <= 4'd0;
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word_ctr <= 4'd0;
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word_ctr <= 4'd0;
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sector_ctr <= 4'd0;
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sector_ctr <= 4'd0;
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digit_idx <= 10'd599;
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digit_idx <= 10'd599;
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early_idx <= 4'd10;
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early_idx <= 4'd0;
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ontime_idx <= 4'd11;
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ontime_idx <= 4'd11;
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end else begin
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end else begin
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digit_idx <= (digit_idx + 1) % 600;
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digit_idx <= (digit_idx + 1) % 600;
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early_idx <= (early_idx + 1) % 12;
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early_idx <= (early_idx + 1) % 12;
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ontime_idx <= (ontime_idx + 1) % 12;
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ontime_idx <= (ontime_idx + 1) % 12;
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digit_ctr <= (digit_ctr + 1) % 12;
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digit_ctr <= (digit_ctr + 1) % 12;
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if (digit_ctr == 4'd11) begin
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if (digit_ctr == 4'd11) begin
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word_ctr <= (word_ctr + 1) % 10;
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word_ctr <= (word_ctr + 1) % 10;
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if (word_ctr == 9) begin
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if (word_ctr == 9) begin
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sector_ctr <= (sector_ctr + 1) % 5;
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sector_ctr <= (sector_ctr + 1) % 5;
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end;
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end;
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end;
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end;
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case (digit_ctr)
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case (digit_ctr)
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4'd0: begin
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4'd0: begin
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d10 <= 0; dx <= 1;
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d10 <= 0; dx <= 1;
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d5_dx <= 0;
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d5_dx <= 0;
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d1_dx <= 0;
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d1_dx <= 0;
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d10_d1_d5 <= 0;
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d10_d1_d5 <= 0;
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wl <= ~word_ctr[3];
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wl <= ~word_ctr[3];
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wu <= word_ctr[3];
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wu <= word_ctr[3];
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case (word_ctr)
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case (word_ctr)
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4'd0: begin
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4'd0: begin
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w9 <= 0; w0 <= 1;
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w9 <= 0; w0 <= 1;
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case (sector_ctr)
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case (sector_ctr)
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3'd0: begin
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3'd0: begin
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s4 <= 0; s0 <= 1;
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s4 <= 0; s0 <= 1;
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hp <= 1;
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hp <= 1;
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end
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end
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3'd1: begin
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3'd1: begin
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s0 <= 0; s1 <= 1;
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s0 <= 0; s1 <= 1;
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end
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end
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3'd2: begin
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3'd2: begin
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s1 <= 0; s2 <= 1;
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s1 <= 0; s2 <= 1;
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end
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end
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3'd3: begin
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3'd3: begin
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s2 <= 0; s3 <= 1;
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s2 <= 0; s3 <= 1;
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end
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end
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3'd4: begin
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3'd4: begin
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s3 <= 0; s4 <= 1;
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s3 <= 0; s4 <= 1;
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end
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end
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endcase;
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endcase;
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end
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end
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4'd1: begin
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4'd1: begin
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w0 <= 0; w1 <= 1;
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w0 <= 0; w1 <= 1;
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end
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end
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4'd2: begin
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4'd2: begin
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w1 <= 0; w2 <= 1;
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w1 <= 0; w2 <= 1;
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end
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end
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4'd3: begin
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4'd3: begin
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w2 <= 0; w3 <= 1;
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w2 <= 0; w3 <= 1;
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end
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end
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4'd4: begin
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4'd4: begin
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w3 <= 0; w4 <= 1;
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w3 <= 0; w4 <= 1;
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end
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end
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4'd5: begin
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4'd5: begin
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w4 <= 0; w5 <= 1;
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w4 <= 0; w5 <= 1;
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end
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end
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4'd6: begin
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4'd6: begin
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w5 <= 0; w6 <= 1;
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w5 <= 0; w6 <= 1;
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end
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end
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4'd7: begin
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4'd7: begin
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w6 <= 0; w7 <= 1;
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w6 <= 0; w7 <= 1;
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end
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end
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4'd8: begin
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4'd8: begin
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w7 <= 0; w8 <= 1;
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w7 <= 0; w8 <= 1;
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end
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end
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4'd9: begin
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4'd9: begin
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w8 <= 0; w9 <= 1;
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w8 <= 0; w9 <= 1;
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end
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end
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endcase;
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endcase;
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end
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end
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4'd1: begin
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4'd1: begin
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dx <= 0; d0 <= 1;
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dx <= 0; d0 <= 1;
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hp <= 0;
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hp <= 0;
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end
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end
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4'd2: begin
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4'd2: begin
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d0 <= 0; d1 <= 1;
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d0 <= 0; d1 <= 1;
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d1_d5 <= 1;
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d1_d5 <= 1;
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end
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end
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4'd3: begin
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4'd3: begin
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d1 <= 0; d2 <= 1;
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d1 <= 0; d2 <= 1;
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d1_dx <= 1;
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d1_dx <= 1;
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d10_d1_d5 <= 1;
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d10_d1_d5 <= 1;
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end
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end
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4'd4: begin
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4'd4: begin
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d2 <= 0; d3 <= 1;
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d2 <= 0; d3 <= 1;
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end
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end
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4'd5: begin
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4'd5: begin
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d3 <= 0; d4 <= 1;
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d3 <= 0; d4 <= 1;
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ewl <= wu;
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ewl <= wu;
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end
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end
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4'd6: begin
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4'd6: begin
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d4 <= 0; d5 <= 1;
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d4 <= 0; d5 <= 1;
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d1_d5 <= 0;
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d1_d5 <= 0;
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d10_d1_d5 <= 0;
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d10_d1_d5 <= 0;
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d5_dx <= 1;
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d5_dx <= 1;
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d5_d10 <= 1;
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d5_d10 <= 1;
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d5_d9 <= 1;
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d5_d9 <= 1;
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end
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end
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4'd7: begin
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4'd7: begin
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d5 <= 0; d6 <= 1;
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d5 <= 0; d6 <= 1;
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end
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end
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4'd8: begin
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4'd8: begin
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d6 <= 0; d7 <= 1;
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d6 <= 0; d7 <= 1;
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end
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end
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4'd9: begin
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4'd9: begin
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d7 <= 0; d8 <= 1;
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d7 <= 0; d8 <= 1;
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end
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end
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4'd10: begin
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4'd10: begin
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d8 <= 0; d9 <= 1;
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d8 <= 0; d9 <= 1;
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d5_d9 <= 0;
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d5_d9 <= 0;
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end
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end
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4'd11: begin
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4'd11: begin
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d9 <= 0; d10 <= 1;
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d9 <= 0; d10 <= 1;
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d5_d10 <= 0;
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d5_d10 <= 0;
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d10_d1_d5 <= 1;
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d10_d1_d5 <= 1;
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end
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end
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endcase;
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endcase;
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end;
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end;
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end;
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end;
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endmodule
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endmodule
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