`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// IBM 650 Reconstruction in Verilog (i650)
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// IBM 650 Reconstruction in Verilog (i650)
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//
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//
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
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// http:////www.opencores.org/project,i650
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// http:////www.opencores.org/project,i650
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//
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//
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// Description: Drum code translators.
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// Description: Drum code translators.
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//
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//
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// Additional Comments:
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// Additional Comments: See US 2959351, Fig. 72.
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//
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//
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// Copyright (c) 2015 Robert Abeles
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// Copyright (c) 2015 Robert Abeles
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
|
// and/or modify it under the terms of the GNU Lesser General
|
// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
|
// You should have received a copy of the GNU Lesser General
|
// Public License along with this source; if not, download it
|
// Public License along with this source; if not, download it
|
// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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`include "defines.v"
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|
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module translators (
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module translators (
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input [0:6] dist_early_out, bs_out, console_out,
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input [0:6] dist_early_out, bs_out, console_out,
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input ri_gs, ri_bs, ri_console,
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input ri_gs, ri_bs, ri_console,
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input n800x,
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input n800x, console_read_gs,
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input [0:4] gs_out,
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input [0:4] gs_out,
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output gs_write,
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output gs_write,
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output [0:4] gs_in,
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output [0:4] gs_in,
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output reg[0:6] select_out
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output reg[0:6] gs_biq_out
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);
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);
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|
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reg [0:6] sel_in7;
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reg [0:6] sel_in7;
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wire [0:6] sel_out7;
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wire [0:6] sel_out7;
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xlate7to5 x75 (sel_in7, gs_in);
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xlate7to5 x75 (sel_in7, gs_in);
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xlate5to7 x57 (gs_out, sel_out7);
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xlate5to7 x57 (gs_out, sel_out7);
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|
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assign gs_write = ri_gs | ri_bs | ri_console;
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assign gs_write = ri_gs | ri_bs | ri_console;
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|
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always @(*) begin
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always @(*) begin
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sel_in7 = ri_console? console_out
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sel_in7 = ri_console? console_out
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: ri_gs? dist_early_out
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: ri_gs? dist_early_out
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: ri_bs? bs_out
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: ri_bs? bs_out
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: `biq_blank;
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: `biq_blank;
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select_out = (n800x)? sel_out7 : `biq_blank;
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gs_biq_out = (n800x | console_read_gs)? sel_out7 : `biq_blank;
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end;
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end;
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|
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endmodule
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endmodule
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|
|
