`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 00:16:54 11/16/2009
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// Create Date: 00:16:54 11/16/2009
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// Design Name: i8255
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// Design Name: i8255
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// Module Name: /home/malasar/projects/fpga/i8080/tsti8255.v
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// Module Name: /home/malasar/projects/fpga/i8080/tsti8255.v
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// Project Name: i8080
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// Project Name: i8080
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: i8255
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// Verilog Test Fixture created by ISE for module: i8255
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module tsti8255;
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module tsti8255;
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// Inputs
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// Inputs
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reg reset;
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reg reset;
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reg ncs;
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reg ncs;
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reg nrd;
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reg nrd;
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reg nwr;
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reg nwr;
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reg [1:0] addr;
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reg [1:0] addr;
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// Bidirs
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// Bidirs
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wire [7:0] data;
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wire [7:0] data;
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wire [7:0] pa;
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wire [7:0] pa;
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reg pae;
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reg pae;
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wire [7:0] pb;
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wire [7:0] pb;
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reg pbe;
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reg pbe;
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wire [3:0] pch;
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wire [3:0] pch;
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reg pche;
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reg pche;
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wire [3:0] pcl;
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wire [3:0] pcl;
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reg pcle;
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reg pcle;
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wire clk;
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wire clk;
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reg oflag;
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reg oflag;
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reg pause;
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reg pause;
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reg [7:0] newval;
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reg [7:0] newval;
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reg [7:0] step;
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reg [7:0] step;
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reg [7:0] wrtport;
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reg [7:0] wrtport;
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reg [7:0] resetret;
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reg [7:0] resetret;
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reg [7:0] writeret;
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reg [7:0] writeret;
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clck clk1(clk);
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clck clk1(clk);
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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i8255 uut (
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i8255 uut (
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.data(data),
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.data(data),
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.reset(reset),
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.reset(reset),
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.ncs(ncs),
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.ncs(ncs),
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.nrd(nrd),
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.nrd(nrd),
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.nwr(nwr),
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.nwr(nwr),
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.addr(addr),
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.addr(addr),
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.pa(pa),
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.pa(pa),
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.pb(pb),
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.pb(pb),
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.pch(pch),
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.pch(pch),
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.pcl(pcl)
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.pcl(pcl)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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reset <= 1;
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reset <= 1;
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pae<=0;
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pae<=0;
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pche<=0;
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pche<=0;
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wrtport<=0;
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wrtport<=0;
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pause<=0;
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ncs <= 1;
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ncs <= 1;
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nrd <= 1;
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nrd <= 1;
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nwr <= 1;
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nwr <= 1;
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addr <= 2'b11;
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addr <= 2'b11;
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oflag<=0;
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oflag<=0;
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newval<=0;
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newval<=0;
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step<=6;
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step<=6;
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resetret<=0;
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resetret<=0;
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writeret<=0;
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writeret<=0;
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#10 $finish();
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#10 $finish();
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// Add stimulus here
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// Add stimulus here
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end
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end
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assign data=(oflag)?newval:8'bz;
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assign data=(oflag)?newval:8'bz;
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assign pa=(pae)?wrtport:8'bz;
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assign pa=(pae)?wrtport:8'bz;
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assign pch=(pche)?wrtport[7:4]:8'bz;
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assign pch=(pche)?wrtport[7:4]:8'bz;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset==1) begin
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if (reset==1) begin
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ncs<=0;
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ncs<=0;
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reset<=0; //#2
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reset<=0; //#2
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end
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end
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else begin
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else begin
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case (step)
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case (step)
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0: begin
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0: begin
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newval<=8'b10000000; //#4
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newval<=8'b10000000; //#4
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oflag<=1;
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oflag<=1;
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step<=33;
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step<=33;
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resetret<=2;
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resetret<=2;
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writeret<=32;
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writeret<=32;
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ncs<=0;
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ncs<=0;
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end
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end
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2: begin
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2: begin
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newval<=8'h35; //#10
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newval<=8'h35; //#10
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oflag<=1;
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oflag<=1;
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addr<=0;
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addr<=0;
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step<=33;
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step<=33;
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resetret<=3;
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resetret<=3;
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writeret<=32;
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writeret<=32;
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end
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end
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3: begin
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3: begin
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newval=8'h0;
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newval<=8'h0;
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nrd=1;
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nrd<=1;
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nwr=1;
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nwr<=1;
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step=4;
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step<=4;
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end
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end
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4: begin
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4: begin
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newval=8'b10100000;
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newval<=8'b10100000;
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addr=2;
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addr<=2;
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nrd=1;
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nrd<=1;
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nwr=0;
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nwr<=0;
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step=5;
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step<=5;
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end
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end
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6: begin
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6: begin
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newval=8'b10010000; //a-output, c -input //#4
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newval<=8'b10010000; //a-output, c -input //#4
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addr=3;
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addr<=3;
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oflag=1;
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oflag<=1;
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pae=0;
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pae<=0;
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step=33;
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step<=33;
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resetret=7;
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resetret<=7;
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writeret=32;
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writeret<=32;
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end
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end
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7: begin
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7: begin
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wrtport=8'b11010000; //#10
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wrtport<=8'b11010000; //#10
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pae=1;
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pae<=1;
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//pche=1;
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//pche=1;
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oflag=0;
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oflag<=0;
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addr=0;
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addr<=0;
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nrd=0;
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nrd<=0;
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nwr=1;
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nwr<=1;
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step=32;
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step<=32;
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resetret=8;
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resetret<=8;
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end
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end
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8: begin
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8: begin
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newval=8'b10100000;
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newval<=8'b10100000;
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//pae=0;
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//pae=0;
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pche=1;
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pche<=1;
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oflag=1;
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oflag<=1;
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addr=0;
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addr<=0;
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nrd=1;
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nrd<=1;
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nwr=0;
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nwr<=0;
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step=10;
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step<=10;
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end
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end
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9: begin
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9: begin
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pae=0;
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pae<=0;
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addr=0;
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addr<=0;
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nrd=0;
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nrd<=0;
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nwr=1;
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nwr<=1;
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step=10;
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step<=10;
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end
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end
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32: begin
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32: begin //reset step
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oflag=0;
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oflag<=0;
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nrd=1;
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nrd<=1;
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nwr=1;
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nwr<=1;
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step=resetret;
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step<=resetret;
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end
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end
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33: begin //write routine
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33: begin //write routine
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nwr=0;
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nwr<=0;
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nrd=1;
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nrd<=1;
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step=writeret;
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step<=writeret;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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endmodule
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endmodule
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