-- VHDL data flow description generated from `count5`
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-- VHDL data flow description generated from `count5`
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-- date : Thu Aug 2 08:47:45 2001
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-- date : Thu Aug 2 08:47:45 2001
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-- Entity Declaration
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-- Entity Declaration
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ENTITY count5 IS
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ENTITY count5 IS
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PORT (
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PORT (
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clk : in BIT; -- clk
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clk : in BIT; -- clk
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rst : in BIT; -- rst
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rst : in BIT; -- rst
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q : out bit_vector(4 DOWNTO 0) ; -- q
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q : out bit_vector(4 DOWNTO 0) ; -- q
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END count5;
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END count5;
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-- Architecture Declaration
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-- Architecture Declaration
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ARCHITECTURE behaviour_data_flow OF count5 IS
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ARCHITECTURE behaviour_data_flow OF count5 IS
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SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER; -- current_state
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SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER; -- current_state
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SIGNAL aux51 : BIT; -- aux51
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SIGNAL aux51 : BIT; -- aux51
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SIGNAL aux48 : BIT; -- aux48
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SIGNAL aux48 : BIT; -- aux48
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SIGNAL aux46 : BIT; -- aux46
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SIGNAL aux46 : BIT; -- aux46
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SIGNAL aux45 : BIT; -- aux45
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SIGNAL aux45 : BIT; -- aux45
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BEGIN
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BEGIN
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aux45 <= (current_state (2) and current_state (1));
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aux45 <= (current_state (2) and current_state (1));
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aux46 <= (not (current_state (1)) or current_state (2));
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aux46 <= (not (current_state (1)) or current_state (2));
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aux48 <= not ((not (current_state (3)) and not (current_state (2))));
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aux48 <= not ((not (current_state (3)) and not (current_state (2))));
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aux51 <= (not (current_state (2)) and current_state (3));
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aux51 <= (not (current_state (2)) and current_state (3));
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label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
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label0 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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BEGIN
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current_state (0) <= GUARDED (rst or (not (current_state (0)) and current_state (3) and not
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current_state (0) <= GUARDED (rst or (not (current_state (0)) and current_state (3) and not
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(current_state (1)) and current_state (2)) or (current_state
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(current_state (1)) and current_state (2)) or (current_state
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(4) and current_state (1) and aux48) or (not (current_state
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(4) and current_state (1) and aux48) or (not (current_state
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(4)) and not (current_state (1)) and not ((current_state (3)
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(4)) and not (current_state (1)) and not ((current_state (3)
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xor current_state (2)))) or (current_state (0) and (not (current_state
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xor current_state (2)))) or (current_state (0) and (not (current_state
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(3)) or not (current_state (2))) and (current_state (4) or aux45)));
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(3)) or not (current_state (2))) and (current_state (4) or aux45)));
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END BLOCK label0;
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END BLOCK label0;
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label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
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label1 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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BEGIN
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current_state (1) <= GUARDED (rst or (current_state (0) and ((not (current_state (1)) and
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current_state (1) <= GUARDED (rst or (current_state (0) and ((not (current_state (1)) and
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aux48) or (current_state (4) and not ((not (current_state (3))
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aux48) or (current_state (4) and not ((not (current_state (3))
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or not (current_state (2))))))) or (not (current_state (0))
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or not (current_state (2))))))) or (not (current_state (0))
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and (current_state (4) or not ((current_state (3) or current_state
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and (current_state (4) or not ((current_state (3) or current_state
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(1))) or aux51) and (not (current_state (4)) or not ((not (current_state
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(1))) or aux51) and (not (current_state (4)) or not ((not (current_state
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(1)) and (not (current_state (2)) or current_state (3)))))));
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(1)) and (not (current_state (2)) or current_state (3)))))));
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END BLOCK label1;
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END BLOCK label1;
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label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
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label2 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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BEGIN
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current_state (2) <= GUARDED (rst or (current_state (4) and not (current_state (3)) and not
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current_state (2) <= GUARDED (rst or (current_state (4) and not (current_state (3)) and not
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(current_state (1)) and current_state (2)) or (not (current_state
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(current_state (1)) and current_state (2)) or (not (current_state
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(4)) and not ((current_state (1) xor aux48))) or (current_state
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(4)) and not ((current_state (1) xor aux48))) or (current_state
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(0) and (not ((not (current_state (2)) or current_state (3)))
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(0) and (not ((not (current_state (2)) or current_state (3)))
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or (current_state (3) and not ((not (current_state (1)) and
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or (current_state (3) and not ((not (current_state (1)) and
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current_state (2)))))));
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current_state (2)))))));
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END BLOCK label2;
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END BLOCK label2;
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label3 : BLOCK ((clk and not (clk'STABLE)) = '1')
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label3 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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BEGIN
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current_state (3) <= GUARDED (rst or (current_state (0) and (not ((not (current_state (3))
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current_state (3) <= GUARDED (rst or (current_state (0) and (not ((not (current_state (3))
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or (not (current_state (2)) and not (current_state (1))))) or
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or (not (current_state (2)) and not (current_state (1))))) or
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not ((current_state (4) or aux45)))) or (not (current_state
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not ((current_state (4) or aux45)))) or (not (current_state
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(0)) and ((not (current_state (4)) and not (current_state (1))
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(0)) and ((not (current_state (4)) and not (current_state (1))
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and not (aux51)) or (current_state (4) and current_state (3)
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and not (aux51)) or (current_state (4) and current_state (3)
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and aux46))));
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and aux46))));
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END BLOCK label3;
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END BLOCK label3;
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label4 : BLOCK ((clk and not (clk'STABLE)) = '1')
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label4 : BLOCK ((clk and not (clk'STABLE)) = '1')
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BEGIN
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BEGIN
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current_state (4) <= GUARDED (rst or ((not (aux46) or (not (current_state (3)) and not (current_state
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current_state (4) <= GUARDED (rst or ((not (aux46) or (not (current_state (3)) and not (current_state
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(1)) and current_state (2)) or not ((not (current_state (4))
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(1)) and current_state (2)) or not ((not (current_state (4))
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and (current_state (0) or (not (current_state (3)) and current_state
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and (current_state (0) or (not (current_state (3)) and current_state
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(1)))))) and (not (current_state (4)) or (not (current_state
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(1)))))) and (not (current_state (4)) or (not (current_state
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(0)) and aux45) or (current_state (0) and (aux51 or (not (current_state
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(0)) and aux45) or (current_state (0) and (aux51 or (not (current_state
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(3)) and current_state (1)))))));
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(3)) and current_state (1)))))));
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END BLOCK label4;
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END BLOCK label4;
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q (0) <= (not (rst) and ((not (current_state (3)) and not (current_state
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q (0) <= (not (rst) and ((not (current_state (3)) and not (current_state
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(1)) and current_state (2)) or (not (current_state (2)) and
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(1)) and current_state (2)) or (not (current_state (2)) and
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current_state (0) and (current_state (3) or current_state (1)))
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current_state (0) and (current_state (3) or current_state (1)))
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or (not (current_state (4)) and (not (current_state (2)) or
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or (not (current_state (4)) and (not (current_state (2)) or
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(current_state (3) and current_state (1) and current_state (0))))));
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(current_state (3) and current_state (1) and current_state (0))))));
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q (1) <= (not (rst) and (not (current_state (0)) or current_state (4)
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q (1) <= (not (rst) and (not (current_state (0)) or current_state (4)
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or not (current_state (3)) or (not (current_state (2)) and not
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or not (current_state (3)) or (not (current_state (2)) and not
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(current_state (1)))) and ((not (current_state (1)) and (not
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(current_state (1)))) and ((not (current_state (1)) and (not
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(current_state (2)) or current_state (3))) or (not (current_state
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(current_state (2)) or current_state (3))) or (not (current_state
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(4)) and (current_state (3) xor current_state (2)))));
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(4)) and (current_state (3) xor current_state (2)))));
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q (2) <= (not (rst) and (not (current_state (0)) or current_state (4)
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q (2) <= (not (rst) and (not (current_state (0)) or current_state (4)
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or aux46) and (not (current_state (3)) or (not (current_state
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or aux46) and (not (current_state (3)) or (not (current_state
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(0)) and not (current_state (4)) and aux45)));
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(0)) and not (current_state (4)) and aux45)));
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q (3) <= ((not (rst) and current_state (4) and current_state (0) and current_state
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q (3) <= ((not (rst) and current_state (4) and current_state (0) and current_state
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(3) and (current_state (2) xor current_state (1))) or (not (rst)
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(3) and (current_state (2) xor current_state (1))) or (not (rst)
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and (not (current_state (0)) or not (aux48)) and (not (current_state
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and (not (current_state (0)) or not (aux48)) and (not (current_state
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(2)) or current_state (0) or (current_state (4) and current_state
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(2)) or current_state (0) or (current_state (4) and current_state
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(1)))));
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(1)))));
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q (4) <= ((not (rst) and not (current_state (0)) and current_state (4)
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q (4) <= ((not (rst) and not (current_state (0)) and current_state (4)
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and not (aux45)) or (not (rst) and not ((not (current_state
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and not (aux45)) or (not (rst) and not ((not (current_state
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(0)) or current_state (4))) and ((not (current_state (1)) and
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(0)) or current_state (4))) and ((not (current_state (1)) and
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current_state (3)) or not (aux46))) or (not (current_state (4))
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current_state (3)) or not (aux46))) or (not (current_state (4))
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and not (rst) and not (current_state (0)) and not ((current_state
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and not (rst) and not (current_state (0)) and not ((current_state
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(3) and (current_state (2) xor current_state (1))))));
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(3) and (current_state (2) xor current_state (1))))));
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END;
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END;
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