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--==============================================================================
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--==============================================================================
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-- |
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-- |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- |
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-- |
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-- Module: Top level of IICMB controller with Avalon-MM interface. |
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-- Module: Top level of IICMB controller with Avalon-MM interface. |
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-- Version: |
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-- Version: |
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-- 1.0, April 29, 2016 |
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-- 1.0, April 29, 2016 |
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-- |
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-- |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- |
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-- |
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--==============================================================================
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--==============================================================================
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- All rights reserved. |
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-- All rights reserved. |
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-- |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions are met: |
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-- modification, are permitted provided that the following conditions are met: |
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-- |
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-- |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- this list of conditions and the following disclaimer. |
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-- this list of conditions and the following disclaimer. |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in the |
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-- notice, this list of conditions and the following disclaimer in the |
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-- documentation and/or other materials provided with the distribution. |
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-- documentation and/or other materials provided with the distribution. |
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-- |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- POSSIBILITY OF SUCH DAMAGE. |
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-- POSSIBILITY OF SUCH DAMAGE. |
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--==============================================================================
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--==============================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--==============================================================================
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--==============================================================================
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entity iicmb_m_av is
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entity iicmb_m_av is
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generic
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generic
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(
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(
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------------------------------------
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------------------------------------
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g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses
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g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses
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g_f_clk : real := 100000.0; -- Frequency of system clock 'clk' (in kHz)
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g_f_clk : real := 100000.0; -- Frequency of system clock 'clk' (in kHz)
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g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz)
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g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz)
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g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz)
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g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz)
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g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz)
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g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz)
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g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz)
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g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz)
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g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz)
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g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz)
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g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz)
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g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz)
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g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz)
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g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz)
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g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz)
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g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz)
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g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz)
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g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz)
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g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz)
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g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz)
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g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz)
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g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz)
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g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz)
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g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz)
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g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz)
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g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz)
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g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz)
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g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz)
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g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz)
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g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz)
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g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz)
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g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz)
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------------------------------------
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------------------------------------
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);
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);
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port
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port
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(
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(
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------------------------------------
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------------------------------------
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-- Avalon-MM signals:
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-- Avalon-MM signals:
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clk : in std_logic; -- Clock
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clk : in std_logic; -- Clock
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s_rst : in std_logic; -- Synchronous reset (active high)
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s_rst : in std_logic; -- Synchronous reset (active high)
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-------------
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-------------
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waitrequest : out std_logic;
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waitrequest : out std_logic; -- Wait request
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readdata : out std_logic_vector(31 downto 0);
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readdata : out std_logic_vector(31 downto 0); -- Data from slave to master
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readdatavalid : out std_logic;
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readdatavalid : out std_logic; -- Data validity indication
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writedata : in std_logic_vector(31 downto 0);
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writedata : in std_logic_vector(31 downto 0); -- Data from master to slave
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write : in std_logic;
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write : in std_logic; -- Asserted to indicate write transfer
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read : in std_logic;
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read : in std_logic; -- Asserted to indicate read transfer
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byteenable : in std_logic_vector( 3 downto 0);
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byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s)
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
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-- Interrupt request:
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-- Interrupt request:
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irq : out std_logic; -- Interrupt request
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irq : out std_logic; -- Interrupt request
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
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-- I2C interfaces:
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-- I2C interfaces:
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scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs
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scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs
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sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs
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sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs
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scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs
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scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs
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sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs
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sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs
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------------------------------------
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------------------------------------
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);
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);
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end entity iicmb_m_av;
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end entity iicmb_m_av;
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--==============================================================================
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--==============================================================================
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--==============================================================================
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--==============================================================================
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architecture str of iicmb_m_av is
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architecture str of iicmb_m_av is
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component avalon_mm is
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component avalon_mm is
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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s_rst : in std_logic;
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s_rst : in std_logic;
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waitrequest : out std_logic;
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waitrequest : out std_logic;
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readdata : out std_logic_vector(31 downto 0);
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readdata : out std_logic_vector(31 downto 0);
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readdatavalid : out std_logic;
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readdatavalid : out std_logic;
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writedata : in std_logic_vector(31 downto 0);
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writedata : in std_logic_vector(31 downto 0);
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write : in std_logic;
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write : in std_logic;
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read : in std_logic;
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read : in std_logic;
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byteenable : in std_logic_vector( 3 downto 0);
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byteenable : in std_logic_vector( 3 downto 0);
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wr : out std_logic_vector( 3 downto 0);
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wr : out std_logic_vector( 3 downto 0);
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rd : out std_logic_vector( 3 downto 0);
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rd : out std_logic_vector( 3 downto 0);
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idata : out std_logic_vector(31 downto 0);
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idata : out std_logic_vector(31 downto 0);
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odata : in std_logic_vector(31 downto 0)
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odata : in std_logic_vector(31 downto 0)
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);
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);
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end component avalon_mm;
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end component avalon_mm;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component regblock is
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component regblock is
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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s_rst : in std_logic;
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s_rst : in std_logic;
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wr : in std_logic_vector( 3 downto 0);
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wr : in std_logic_vector( 3 downto 0);
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rd : in std_logic_vector( 3 downto 0);
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rd : in std_logic_vector( 3 downto 0);
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idata : in std_logic_vector(31 downto 0);
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idata : in std_logic_vector(31 downto 0);
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odata : out std_logic_vector(31 downto 0);
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odata : out std_logic_vector(31 downto 0);
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irq : out std_logic;
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irq : out std_logic;
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busy : in std_logic;
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busy : in std_logic;
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captured : in std_logic;
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captured : in std_logic;
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bus_id : in std_logic_vector( 3 downto 0);
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bus_id : in std_logic_vector( 3 downto 0);
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bit_state : in std_logic_vector( 3 downto 0);
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bit_state : in std_logic_vector( 3 downto 0);
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byte_state : in std_logic_vector( 3 downto 0);
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byte_state : in std_logic_vector( 3 downto 0);
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disable : out std_logic;
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disable : out std_logic;
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mcmd_wr : out std_logic;
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mcmd_wr : out std_logic;
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mcmd_id : out std_logic_vector( 2 downto 0);
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mcmd_id : out std_logic_vector( 2 downto 0);
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mcmd_data : out std_logic_vector( 7 downto 0);
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mcmd_data : out std_logic_vector( 7 downto 0);
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mrsp_wr : in std_logic;
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mrsp_wr : in std_logic;
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mrsp_id : in std_logic_vector( 2 downto 0);
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mrsp_id : in std_logic_vector( 2 downto 0);
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mrsp_data : in std_logic_vector( 7 downto 0)
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mrsp_data : in std_logic_vector( 7 downto 0)
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);
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);
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end component regblock;
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end component regblock;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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component iicmb_m is
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component iicmb_m is
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generic
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generic
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(
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(
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g_bus_num : positive range 1 to 16 := 1;
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g_bus_num : positive range 1 to 16 := 1;
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g_f_clk : real := 100000.0;
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g_f_clk : real := 100000.0;
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g_f_scl_0 : real := 100.0;
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g_f_scl_0 : real := 100.0;
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g_f_scl_1 : real := 100.0;
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g_f_scl_1 : real := 100.0;
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g_f_scl_2 : real := 100.0;
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g_f_scl_2 : real := 100.0;
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g_f_scl_3 : real := 100.0;
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g_f_scl_3 : real := 100.0;
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g_f_scl_4 : real := 100.0;
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g_f_scl_4 : real := 100.0;
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g_f_scl_5 : real := 100.0;
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g_f_scl_5 : real := 100.0;
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g_f_scl_6 : real := 100.0;
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g_f_scl_6 : real := 100.0;
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g_f_scl_7 : real := 100.0;
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g_f_scl_7 : real := 100.0;
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g_f_scl_8 : real := 100.0;
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g_f_scl_8 : real := 100.0;
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g_f_scl_9 : real := 100.0;
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g_f_scl_9 : real := 100.0;
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g_f_scl_a : real := 100.0;
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g_f_scl_a : real := 100.0;
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g_f_scl_b : real := 100.0;
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g_f_scl_b : real := 100.0;
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g_f_scl_c : real := 100.0;
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g_f_scl_c : real := 100.0;
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g_f_scl_d : real := 100.0;
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g_f_scl_d : real := 100.0;
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g_f_scl_e : real := 100.0;
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g_f_scl_e : real := 100.0;
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g_f_scl_f : real := 100.0
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g_f_scl_f : real := 100.0
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);
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);
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port
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port
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(
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(
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clk : in std_logic;
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clk : in std_logic;
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s_rst : in std_logic;
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s_rst : in std_logic;
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busy : out std_logic;
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busy : out std_logic;
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captured : out std_logic;
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captured : out std_logic;
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bus_id : out std_logic_vector(3 downto 0);
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bus_id : out std_logic_vector(3 downto 0);
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bit_state : out std_logic_vector(3 downto 0);
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bit_state : out std_logic_vector(3 downto 0);
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byte_state : out std_logic_vector(3 downto 0);
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byte_state : out std_logic_vector(3 downto 0);
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mcmd_wr : in std_logic;
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mcmd_wr : in std_logic;
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mcmd_id : in std_logic_vector(2 downto 0);
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mcmd_id : in std_logic_vector(2 downto 0);
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mcmd_data : in std_logic_vector(7 downto 0);
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mcmd_data : in std_logic_vector(7 downto 0);
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mrsp_wr : out std_logic;
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mrsp_wr : out std_logic;
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mrsp_id : out std_logic_vector(2 downto 0);
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mrsp_id : out std_logic_vector(2 downto 0);
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mrsp_data : out std_logic_vector(7 downto 0);
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mrsp_data : out std_logic_vector(7 downto 0);
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scl_i : in std_logic_vector(0 to g_bus_num - 1);
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scl_i : in std_logic_vector(0 to g_bus_num - 1);
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sda_i : in std_logic_vector(0 to g_bus_num - 1);
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sda_i : in std_logic_vector(0 to g_bus_num - 1);
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scl_o : out std_logic_vector(0 to g_bus_num - 1);
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scl_o : out std_logic_vector(0 to g_bus_num - 1);
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sda_o : out std_logic_vector(0 to g_bus_num - 1)
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sda_o : out std_logic_vector(0 to g_bus_num - 1)
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);
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);
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end component iicmb_m;
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end component iicmb_m;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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|
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signal wr : std_logic_vector( 3 downto 0);
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signal wr : std_logic_vector( 3 downto 0);
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signal rd : std_logic_vector( 3 downto 0);
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signal rd : std_logic_vector( 3 downto 0);
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signal idata : std_logic_vector(31 downto 0);
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signal idata : std_logic_vector(31 downto 0);
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signal odata : std_logic_vector(31 downto 0);
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signal odata : std_logic_vector(31 downto 0);
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|
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signal busy : std_logic;
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signal busy : std_logic;
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signal captured : std_logic;
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signal captured : std_logic;
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signal bus_id : std_logic_vector( 3 downto 0);
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signal bus_id : std_logic_vector( 3 downto 0);
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signal bit_state : std_logic_vector( 3 downto 0);
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signal bit_state : std_logic_vector( 3 downto 0);
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signal byte_state : std_logic_vector( 3 downto 0);
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signal byte_state : std_logic_vector( 3 downto 0);
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signal disable : std_logic; -- used as synchronous reset for 'iicmb_m'
|
signal disable : std_logic; -- used as synchronous reset for 'iicmb_m'
|
|
|
-- Signals of 'Generic Interface':
|
-- Signals of 'Generic Interface':
|
-- Command:
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-- Command:
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signal mcmd_wr : std_logic;
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signal mcmd_wr : std_logic;
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signal mcmd_id : std_logic_vector( 2 downto 0);
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signal mcmd_id : std_logic_vector( 2 downto 0);
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signal mcmd_data : std_logic_vector( 7 downto 0);
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signal mcmd_data : std_logic_vector( 7 downto 0);
|
-- Response:
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-- Response:
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signal mrsp_wr : std_logic;
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signal mrsp_wr : std_logic;
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signal mrsp_id : std_logic_vector( 2 downto 0);
|
signal mrsp_id : std_logic_vector( 2 downto 0);
|
signal mrsp_data : std_logic_vector( 7 downto 0);
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signal mrsp_data : std_logic_vector( 7 downto 0);
|
|
|
begin
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begin
|
|
|
------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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avalon_mm_inst0 : avalon_mm
|
avalon_mm_inst0 : avalon_mm
|
port map
|
port map
|
(
|
(
|
clk => clk,
|
clk => clk,
|
s_rst => s_rst,
|
s_rst => s_rst,
|
waitrequest => waitrequest,
|
waitrequest => waitrequest,
|
readdata => readdata,
|
readdata => readdata,
|
readdatavalid => readdatavalid,
|
readdatavalid => readdatavalid,
|
writedata => writedata,
|
writedata => writedata,
|
write => write,
|
write => write,
|
read => read,
|
read => read,
|
byteenable => byteenable,
|
byteenable => byteenable,
|
wr => wr,
|
wr => wr,
|
rd => rd,
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rd => rd,
|
idata => idata,
|
idata => idata,
|
odata => odata
|
odata => odata
|
);
|
);
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
regblock_inst9 : regblock
|
regblock_inst9 : regblock
|
port map
|
port map
|
(
|
(
|
clk => clk,
|
clk => clk,
|
s_rst => s_rst,
|
s_rst => s_rst,
|
wr => wr,
|
wr => wr,
|
rd => rd,
|
rd => rd,
|
idata => idata,
|
idata => idata,
|
odata => odata,
|
odata => odata,
|
irq => irq,
|
irq => irq,
|
busy => busy,
|
busy => busy,
|
captured => captured,
|
captured => captured,
|
bus_id => bus_id,
|
bus_id => bus_id,
|
bit_state => bit_state,
|
bit_state => bit_state,
|
byte_state => byte_state,
|
byte_state => byte_state,
|
disable => disable,
|
disable => disable,
|
mcmd_wr => mcmd_wr,
|
mcmd_wr => mcmd_wr,
|
mcmd_id => mcmd_id,
|
mcmd_id => mcmd_id,
|
mcmd_data => mcmd_data,
|
mcmd_data => mcmd_data,
|
mrsp_wr => mrsp_wr,
|
mrsp_wr => mrsp_wr,
|
mrsp_id => mrsp_id,
|
mrsp_id => mrsp_id,
|
mrsp_data => mrsp_data
|
mrsp_data => mrsp_data
|
);
|
);
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
iicmb_m_inst0 : iicmb_m
|
iicmb_m_inst0 : iicmb_m
|
generic map
|
generic map
|
(
|
(
|
g_bus_num => g_bus_num,
|
g_bus_num => g_bus_num,
|
g_f_clk => g_f_clk,
|
g_f_clk => g_f_clk,
|
g_f_scl_0 => g_f_scl_0,
|
g_f_scl_0 => g_f_scl_0,
|
g_f_scl_1 => g_f_scl_1,
|
g_f_scl_1 => g_f_scl_1,
|
g_f_scl_2 => g_f_scl_2,
|
g_f_scl_2 => g_f_scl_2,
|
g_f_scl_3 => g_f_scl_3,
|
g_f_scl_3 => g_f_scl_3,
|
g_f_scl_4 => g_f_scl_4,
|
g_f_scl_4 => g_f_scl_4,
|
g_f_scl_5 => g_f_scl_5,
|
g_f_scl_5 => g_f_scl_5,
|
g_f_scl_6 => g_f_scl_6,
|
g_f_scl_6 => g_f_scl_6,
|
g_f_scl_7 => g_f_scl_7,
|
g_f_scl_7 => g_f_scl_7,
|
g_f_scl_8 => g_f_scl_8,
|
g_f_scl_8 => g_f_scl_8,
|
g_f_scl_9 => g_f_scl_9,
|
g_f_scl_9 => g_f_scl_9,
|
g_f_scl_a => g_f_scl_a,
|
g_f_scl_a => g_f_scl_a,
|
g_f_scl_b => g_f_scl_b,
|
g_f_scl_b => g_f_scl_b,
|
g_f_scl_c => g_f_scl_c,
|
g_f_scl_c => g_f_scl_c,
|
g_f_scl_d => g_f_scl_d,
|
g_f_scl_d => g_f_scl_d,
|
g_f_scl_e => g_f_scl_e,
|
g_f_scl_e => g_f_scl_e,
|
g_f_scl_f => g_f_scl_f
|
g_f_scl_f => g_f_scl_f
|
)
|
)
|
port map
|
port map
|
(
|
(
|
clk => clk,
|
clk => clk,
|
s_rst => disable,
|
s_rst => disable,
|
busy => busy,
|
busy => busy,
|
captured => captured,
|
captured => captured,
|
bus_id => bus_id,
|
bus_id => bus_id,
|
bit_state => bit_state,
|
bit_state => bit_state,
|
byte_state => byte_state,
|
byte_state => byte_state,
|
mcmd_wr => mcmd_wr,
|
mcmd_wr => mcmd_wr,
|
mcmd_id => mcmd_id,
|
mcmd_id => mcmd_id,
|
mcmd_data => mcmd_data,
|
mcmd_data => mcmd_data,
|
mrsp_wr => mrsp_wr,
|
mrsp_wr => mrsp_wr,
|
mrsp_id => mrsp_id,
|
mrsp_id => mrsp_id,
|
mrsp_data => mrsp_data,
|
mrsp_data => mrsp_data,
|
scl_i => scl_i,
|
scl_i => scl_i,
|
sda_i => sda_i,
|
sda_i => sda_i,
|
scl_o => scl_o,
|
scl_o => scl_o,
|
sda_o => sda_o
|
sda_o => sda_o
|
);
|
);
|
------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
|
|
|
end architecture str;
|
end architecture str;
|
--==============================================================================
|
--==============================================================================
|
|
|
|
|