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--==============================================================================
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--==============================================================================
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-- |
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-- |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- Project: IIC Multiple Bus Controller (IICMB) |
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-- |
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-- |
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-- Module: Wishbone adapter. |
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-- Module: Wishbone adapter. |
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-- Version: |
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-- Version: |
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-- 1.0, April 29, 2016 |
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-- 1.0, April 29, 2016 |
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-- |
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-- |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) |
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-- |
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-- |
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--==============================================================================
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--==============================================================================
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--==============================================================================
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--==============================================================================
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- Copyright (c) 2016, Sergey Shuvalkin |
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-- All rights reserved. |
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-- All rights reserved. |
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-- |
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-- |
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-- Redistribution and use in source and binary forms, with or without |
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-- Redistribution and use in source and binary forms, with or without |
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-- modification, are permitted provided that the following conditions are met: |
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-- modification, are permitted provided that the following conditions are met: |
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-- |
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-- |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- 1. Redistributions of source code must retain the above copyright notice, |
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-- this list of conditions and the following disclaimer. |
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-- this list of conditions and the following disclaimer. |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- 2. Redistributions in binary form must reproduce the above copyright |
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-- notice, this list of conditions and the following disclaimer in the |
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-- notice, this list of conditions and the following disclaimer in the |
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-- documentation and/or other materials provided with the distribution. |
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-- documentation and/or other materials provided with the distribution. |
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-- |
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-- |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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-- POSSIBILITY OF SUCH DAMAGE. |
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-- POSSIBILITY OF SUCH DAMAGE. |
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--==============================================================================
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--==============================================================================
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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--==============================================================================
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--==============================================================================
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entity wishbone is
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entity wishbone is
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port
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port
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(
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(
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------------------------------------
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------------------------------------
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clk_i : in std_logic; -- Clock input
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clk_i : in std_logic; -- Clock input
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rst_i : in std_logic; -- Synchronous reset (active high)
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rst_i : in std_logic; -- Synchronous reset (active high)
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
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-- Wishbone slave interface:
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-- Wishbone slave interface:
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cyc_i : in std_logic; --
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cyc_i : in std_logic; -- Valid bus cycle indication
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stb_i : in std_logic; --
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stb_i : in std_logic; -- Slave selection
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ack_o : out std_logic; --
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ack_o : out std_logic; -- Acknowledge output
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adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address
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adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address
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we_i : in std_logic; --
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we_i : in std_logic; -- Write enable
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dat_i : in std_logic_vector( 7 downto 0); -- Data input
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dat_i : in std_logic_vector( 7 downto 0); -- Data input
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dat_o : out std_logic_vector( 7 downto 0); -- Data output
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dat_o : out std_logic_vector( 7 downto 0); -- Data output
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------------------------------------
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------------------------------------
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------------------------------------
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------------------------------------
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-- Regblock interface:
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-- Regblock interface:
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wr : out std_logic_vector( 3 downto 0); -- Write (active high)
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wr : out std_logic_vector( 3 downto 0); -- Write (active high)
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rd : out std_logic_vector( 3 downto 0); -- Read (active high)
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rd : out std_logic_vector( 3 downto 0); -- Read (active high)
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idata : out std_logic_vector(31 downto 0); -- Data from System Bus
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idata : out std_logic_vector(31 downto 0); -- Data from System Bus
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odata : in std_logic_vector(31 downto 0) -- Data to System Bus
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odata : in std_logic_vector(31 downto 0) -- Data to System Bus
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------------------------------------
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------------------------------------
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);
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);
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end entity wishbone;
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end entity wishbone;
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--==============================================================================
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--==============================================================================
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--==============================================================================
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--==============================================================================
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architecture rtl of wishbone is
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architecture rtl of wishbone is
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signal ack_o_y : std_logic := '0';
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signal ack_o_y : std_logic := '0';
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signal dat_o_y : std_logic_vector(7 downto 0) := (others => '0');
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signal dat_o_y : std_logic_vector(7 downto 0) := (others => '0');
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begin
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begin
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ack_o <= ack_o_y;
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ack_o <= ack_o_y;
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dat_o <= dat_o_y;
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dat_o <= dat_o_y;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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ack_o_proc:
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ack_o_proc:
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process(clk_i)
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process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (rst_i = '1') then
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if (rst_i = '1') then
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ack_o_y <= '0';
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ack_o_y <= '0';
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else
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else
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if (ack_o_y = '0') then
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if (ack_o_y = '0') then
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ack_o_y <= stb_i and cyc_i;
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ack_o_y <= stb_i and cyc_i;
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else
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else
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ack_o_y <= '0';
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ack_o_y <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process ack_o_proc;
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end process ack_o_proc;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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wr(0) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "00") else '0';
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wr(0) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "00") else '0';
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wr(1) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "01") else '0';
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wr(1) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "01") else '0';
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wr(2) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "10") else '0';
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wr(2) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "10") else '0';
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wr(3) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "11") else '0';
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wr(3) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "11") else '0';
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rd(0) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "00") else '0';
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rd(0) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "00") else '0';
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rd(1) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "01") else '0';
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rd(1) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "01") else '0';
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rd(2) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "10") else '0';
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rd(2) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "10") else '0';
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rd(3) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "11") else '0';
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rd(3) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "11") else '0';
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idata <= dat_i & dat_i & dat_i & dat_i;
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idata <= dat_i & dat_i & dat_i & dat_i;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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dat_o_proc:
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dat_o_proc:
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process(clk_i)
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process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (rst_i = '1') then
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if (rst_i = '1') then
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dat_o_y <= (others => '0');
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dat_o_y <= (others => '0');
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else
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else
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case (adr_i) is
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case (adr_i) is
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when "00" => dat_o_y <= odata( 7 downto 0);
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when "00" => dat_o_y <= odata( 7 downto 0);
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when "01" => dat_o_y <= odata(15 downto 8);
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when "01" => dat_o_y <= odata(15 downto 8);
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when "10" => dat_o_y <= odata(23 downto 16);
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when "10" => dat_o_y <= odata(23 downto 16);
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when others => dat_o_y <= odata(31 downto 24);
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when others => dat_o_y <= odata(31 downto 24);
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process dat_o_proc;
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end process dat_o_proc;
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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end architecture rtl;
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end architecture rtl;
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--==============================================================================
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--==============================================================================
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