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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module accumulatorMUX (accMuxSel, immData, aluOut
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module accumulatorMUX (accMuxSel, immData, aluOut
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, tcLoadIn, tcAccIn
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, tcLoadIn, tcAccIn
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartDataIn, uartStatIn
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, uartDataIn, uartStatIn
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, spiStatIn, spiBufIn
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, spiStatIn, spiBufIn
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`endif
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`endif
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, accMuxOut
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, accMuxOut
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);
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);
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input [`accMuxSelLen-1:0] accMuxSel;
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input [`accMuxSelLen-1:0] accMuxSel;
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input [`immDataLen-1:0] immData;
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input [`immDataLen-1:0] immData;
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input [7:0] aluOut;
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input [7:0] aluOut;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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input [7:0] tcLoadIn, tcAccIn;
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input [7:0] tcLoadIn, tcAccIn;
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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input [7:0] uartDataIn, uartStatIn;
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input [7:0] uartDataIn, uartStatIn;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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input [7:0] spiStatIn, spiBufIn;
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input [7:0] spiStatIn, spiBufIn;
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`endif
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`endif
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output [7:0] accMuxOut;
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output [7:0] accMuxOut;
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reg [7:0] accMuxOut;
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reg [7:0] accMuxOut;
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always @ *
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always @ *
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begin
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begin
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case (accMuxSel)
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case (accMuxSel)
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`accMuxSelImmData : begin
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`accMuxSelImmData : begin
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accMuxOut = immData;
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accMuxOut = immData;
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end
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end
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`accMuxSelAluOut : begin
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`accMuxSelAluOut : begin
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accMuxOut = aluOut;
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accMuxOut = aluOut;
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end
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end
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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`accMuxSelTcLoad : begin
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`accMuxSelTcLoad : begin
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accMuxOut = tcLoadIn;
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accMuxOut = tcLoadIn;
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end
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end
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`accMuxSelTcAcc : begin
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`accMuxSelTcAcc : begin
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accMuxOut = tcAccIn;
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accMuxOut = tcAccIn;
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end
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end
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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`accMuxSelUartData : begin
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`accMuxSelUartData : begin
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accMuxOut = uartDataIn;
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accMuxOut = uartDataIn;
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end
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end
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`accMuxSelUartStat : begin
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`accMuxSelUartStat : begin
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accMuxOut = uartStatIn;
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accMuxOut = uartStatIn;
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end
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end
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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`accMuxSelSpiStat : begin
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`accMuxSelSpiStat : begin
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accMuxOut = spiStatIn;
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accMuxOut = spiStatIn;
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end
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end
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`accMuxSelSpiBuf : begin
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`accMuxSelSpiBuf : begin
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accMuxOut = spiBufIn;
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accMuxOut = spiBufIn;
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end
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end
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`endif
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`endif
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default : begin
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default : begin
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accMuxOut = 8'bzzzzzzzz;
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accMuxOut = 8'bzzzzzzzz;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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