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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
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module alu (input [`aluOpcodeLen-1:0] aluOpcode, input [7:0] op1, input [7:0] op2, input aluEn,
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output [7:0] aluOut, output carryOut);
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output [7:0] aluOut, output carryOut);
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wire [8:0] operand1 = {1'b0, op1};
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wire [8:0] operand1 = {1'b0, op1};
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wire [8:0] operand2 = {1'b0, op2};
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wire [8:0] operand2 = {1'b0, op2};
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wire [8:0] addRes = operand1 + operand2;
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wire [8:0] addRes = operand1 + operand2;
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wire [8:0] subRes = operand1 - operand2;
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wire [8:0] subRes = operand1 - operand2;
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reg [8:0] aluOut = 0;
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reg [8:0] aluOut = 0;
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reg carryOut = 0;
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reg carryOut = 0;
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always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
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always @ (aluEn or addRes or subRes or op1 or op2 or aluOpcode)
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begin
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begin
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if (aluEn)
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if (aluEn)
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begin
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begin
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case (aluOpcode)
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case (aluOpcode)
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`AND_alu : begin
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`AND_alu : begin
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aluOut = op1 & op2;
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aluOut = op1 & op2;
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end
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end
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`OR_alu : begin
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`OR_alu : begin
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aluOut = op1 | op2;
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aluOut = op1 | op2;
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end
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end
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`XOR_alu : begin
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`XOR_alu : begin
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aluOut = op1^op2;
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aluOut = op1^op2;
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end
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end
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`GT_alu : begin
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`GT_alu : begin
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aluOut = op1>op2 ? 1'b1 : 1'b0;
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aluOut = op1>op2 ? 1'b1 : 1'b0;
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end
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end
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`GE_alu : begin
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`GE_alu : begin
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aluOut = op1>=op2 ? 1'b1 : 1'b0;
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aluOut = op1>=op2 ? 1'b1 : 1'b0;
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end
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end
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`EQ_alu : begin
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`EQ_alu : begin
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aluOut = op1==op2 ? 1'b1 : 1'b0;
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aluOut = op1==op2 ? 1'b1 : 1'b0;
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end
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end
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`LE_alu : begin
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`LE_alu : begin
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aluOut = op1<=op2 ? 1'b1 : 1'b0;
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aluOut = op1<=op2 ? 1'b1 : 1'b0;
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end
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end
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`LT_alu : begin
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`LT_alu : begin
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aluOut = op1<op2 ? 1'b1 : 1'b0;
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aluOut = op1<op2 ? 1'b1 : 1'b0;
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end
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end
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`ADD_alu : begin
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`ADD_alu : begin
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aluOut = addRes[7:0];
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aluOut = addRes[7:0];
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carryOut = addRes[8];
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carryOut = addRes[8];
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end
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end
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`SUB_alu : begin
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`SUB_alu : begin
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aluOut = subRes[7:0];
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aluOut = subRes[7:0];
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carryOut = subRes[8];
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carryOut = subRes[8];
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end
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end
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`LD_data : begin
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`LD_data : begin
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aluOut = op2;
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aluOut = op2;
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end
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end
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default : begin
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default : begin
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aluOut = 16'b0;
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aluOut = 16'b0;
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$write ("\nUnknown operation. \tmodule : ALU");
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$write ("\nUnknown operation. \tmodule : ALU");
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end
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end
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endcase
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endcase
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end
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end
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else
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else
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begin
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begin
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aluOut = aluOut;
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aluOut = aluOut;
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end
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end
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end
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end
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endmodule
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endmodule
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