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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module counter (clk, reset, preset, type, DN, CU, CD, ACC);
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module counter (clk, reset, preset, type, DN, CU, CD, ACC);
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input clk, reset;
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input clk, reset;
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input [`tcPresetLen-1:0] preset;
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input [`tcPresetLen-1:0] preset;
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input [`tcTypeLen-1:0] type;
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input [`tcTypeLen-1:0] type;
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output DN, CU, CD;
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output DN, CU, CD;
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output [`tcAccLen-1:0] ACC;
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output [`tcAccLen-1:0] ACC;
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reg DN = 0, CU = 0, CD = 0;
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reg DN = 0, CU = 0, CD = 0;
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reg [`tcAccLen-1:0] ACC = 0;
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reg [`tcAccLen-1:0] ACC = 0;
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reg [`tcTypeLen-1:0] CounterType;
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reg [`tcTypeLen-1:0] CounterType;
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reg [`tcTypeLen-1:0] typeNext;
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reg [`tcTypeLen-1:0] typeNext;
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parameter UpCounter = `tcTypeLen'b01;
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parameter UpCounter = `tcTypeLen'b01;
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parameter DownCounter = `tcTypeLen'b10;
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parameter DownCounter = `tcTypeLen'b10;
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parameter defaultType = `tcTypeLen'b00;
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parameter defaultType = `tcTypeLen'b00;
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always @ (type)
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always @ (type)
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begin
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begin
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case (type)
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case (type)
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`counterType1 : begin
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`counterType1 : begin
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typeNext = UpCounter;
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typeNext = UpCounter;
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end
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end
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`counterType2 : begin
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`counterType2 : begin
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typeNext = DownCounter;
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typeNext = DownCounter;
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end
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end
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default : begin
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default : begin
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$display ("\ncounter is of undefined type.\n Valid types are Up counter & Down counter");
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$display ("\ncounter is of undefined type.\n Valid types are Up counter & Down counter");
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end
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end
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endcase
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endcase
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end
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end
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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$display ("counter module is reset");
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$display ("counter module is reset");
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CounterType = defaultType;
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CounterType = defaultType;
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end
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end
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else
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else
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begin
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begin
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CounterType = typeNext;
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CounterType = typeNext;
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end
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end
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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case (CounterType)
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case (CounterType)
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UpCounter : begin
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UpCounter : begin
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CD = 0; // CD id always 0 for this state
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CD = 0; // CD id always 0 for this state
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if (reset)
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if (reset)
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begin
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begin
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ACC = `tcAccLen-1'b0; // starts at lowest value
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ACC = `tcAccLen-1'b0; // starts at lowest value
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CU = 0;
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CU = 0;
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DN = 0;
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DN = 0;
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end
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end
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else
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else
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begin
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begin
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ACC = ACC + 1'b1;
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ACC = ACC + 1'b1;
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CU = 1'b1;
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CU = 1'b1;
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if (ACC > preset)
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if (ACC > preset)
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begin
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begin
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DN = 1'b1;
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DN = 1'b1;
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end
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end
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end
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end
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end
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end
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DownCounter : begin
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DownCounter : begin
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CU = 0; // CU id always 0 for this state
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CU = 0; // CU id always 0 for this state
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if (reset)
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if (reset)
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begin
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begin
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ACC = `tcAccLen-1'b1; // starts at highest value
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ACC = `tcAccLen-1'b1; // starts at highest value
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CD = 0;
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CD = 0;
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DN = 0;
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DN = 0;
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end
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end
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else
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else
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begin
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begin
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ACC = ACC - 1'b1;
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ACC = ACC - 1'b1;
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CD = 1'b1;
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CD = 1'b1;
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if (ACC < preset)
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if (ACC < preset)
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begin
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begin
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DN = 1'b1;
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DN = 1'b1;
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end
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end
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end
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end
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end
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end
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default : begin
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default : begin
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$display ("\nerror in counter type ");
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$display ("\nerror in counter type ");
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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