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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module outputReg (reset, outputRw, outputRwAddr, outputWriteIn, outputReadOut, outputs);
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module outputReg (reset, outputRw, outputRwAddr, outputWriteIn, outputReadOut, outputs);
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input reset, outputRw;
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input reset, outputRw;
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input [`outputAddrLen-1:0] outputRwAddr;
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input [`outputAddrLen-1:0] outputRwAddr;
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input outputWriteIn;
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input outputWriteIn;
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output outputReadOut;
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output outputReadOut;
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output [`outputNumber-1:0] outputs;
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output [`outputNumber-1:0] outputs;
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reg outputReadOut;
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reg outputReadOut;
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reg [`outputNumber-1:0] outputs = 0;
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reg [`outputNumber-1:0] outputs = 0;
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reg [`outputNumber-1 :0] outputReg = 0;
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reg [`outputNumber-1 :0] outputReg = 0;
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always @ (reset or outputRw or outputRwAddr or outputWriteIn or outputReg)
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always @ (reset or outputRw or outputRwAddr or outputWriteIn or outputReg)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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outputReadOut = 1'bz;
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outputReadOut = 1'bz;
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$write ("\nmodule outputRegister is reset ");
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$write ("\nmodule outputRegister is reset ");
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end
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end
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else
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else
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begin
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begin
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outputs = outputReg;
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outputs = outputReg;
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if (outputRw) // read output status
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if (outputRw) // read output status
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begin
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begin
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outputReadOut = outputReg[outputRwAddr];
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outputReadOut = outputReg[outputRwAddr];
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// $write ("\nreading output register : module outputRegister ");
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// $write ("\nreading output register : module outputRegister ");
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end
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end
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else // write operation
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else // write operation
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begin
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begin
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outputReg[outputRwAddr] = outputWriteIn;
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outputReg[outputRwAddr] = outputWriteIn;
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// $write ("\nwriting to the output register : module outputRegister ");
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// $write ("\nwriting to the output register : module outputRegister ");
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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