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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module pgmCounter (clk, reset, branch, pcIn, pcOut);
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module pgmCounter (clk, reset, branch, pcIn, pcOut);
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input clk, reset, branch;
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input clk, reset, branch;
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input [`instAddrLen-1:0] pcIn;
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input [`instAddrLen-1:0] pcIn;
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output [`instAddrLen-1:0] pcOut;
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output [`instAddrLen-1:0] pcOut;
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reg [`instAddrLen-1:0] pcOut = `instAddrLen'b0;
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reg [`instAddrLen-1:0] pcOut = `instAddrLen'b0;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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pcOut = `instAddrLen'b0;
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pcOut = `instAddrLen'b0;
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$write ("\nprogram counter module is reset. Starting at address 00h ");
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$write ("\nprogram counter module is reset. Starting at address 00h ");
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end
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end
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else
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else
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begin
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begin
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if(branch)
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if(branch)
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begin
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begin
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pcOut = pcIn;
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pcOut = pcIn;
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$write ("\nbranching at address %h", pcIn);
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$write ("\nbranching at address %h", pcIn);
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end
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end
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else
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else
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begin
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begin
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pcOut = pcOut + 1'b1;
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pcOut = pcOut + 1'b1;
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end
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end
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end
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end
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end // end always
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end // end always
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endmodule
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endmodule
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