|
|
`include "timescale.v"
|
`include "timescale.v"
|
`include "defines.v"
|
`include "defines.v"
|
|
|
module bitRam (clk, reset, bitRamEn, bitRamRw, bitRamIn, bitRamAddr, bitRamOut);
|
module bitRam (clk, reset, bitRamEn, bitRamRw, bitRamIn, bitRamAddr, bitRamOut);
|
|
|
|
|
input clk, reset, bitRamEn, bitRamRw, bitRamIn;
|
input clk, reset, bitRamEn, bitRamRw, bitRamIn;
|
input [`bitRamAddrLen-1:0] bitRamAddr;
|
input [`bitRamAddrLen-1:0] bitRamAddr;
|
|
|
output bitRamOut;
|
output bitRamOut;
|
|
|
reg bitRam [`bitRamDepth-1:0];
|
reg bitRam [`bitRamDepth-1:0];
|
reg bitRamOut;
|
reg bitRamOut;
|
|
|
|
|
always @ (posedge clk or posedge reset)
|
always @ (posedge clk or posedge reset)
|
begin
|
begin
|
|
|
if (reset)
|
if (reset)
|
begin
|
begin
|
bitRamOut = 1'b0;
|
bitRamOut = 1'b0;
|
$write (" module bitRam is reset ");
|
$write ("\nmodule bitRam is reset ");
|
end
|
end
|
|
|
else
|
else
|
begin
|
begin
|
|
|
if (bitRamEn)
|
if (bitRamEn)
|
begin
|
begin
|
if (bitRamRw) // read operation
|
if (bitRamRw) // read operation
|
begin
|
begin
|
bitRamOut = bitRam[bitRamAddr];
|
bitRamOut = bitRam[bitRamAddr];
|
$write (" reading bit-RAM : module bitRAM ");
|
// $write ("\nreading bit-RAM : module bitRAM ");
|
end
|
end
|
|
|
else // write operation
|
else // write operation
|
begin
|
begin
|
bitRam[bitRamAddr] = bitRamIn;
|
bitRam[bitRamAddr] = bitRamIn;
|
$write (" writing to bit-RAM : module bitRam ");
|
// $write ("\nwriting to bit-RAM : module bitRam ");
|
end
|
end
|
end
|
end
|
|
|
else
|
else
|
begin
|
begin
|
bitRamOut = 1'bZ;
|
bitRamOut = 1'bZ;
|
end
|
end
|
|
|
end // end else of reset
|
end // end else of reset
|
|
|
end // end always block
|
end // end always block
|
|
|
|
|
endmodule
|
endmodule
|
|
|
