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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module tcEnableAndType (entypeEn, enIn, typeIn, tcAddr, enOut, typeOut);
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module tcEnableAndType (entypeEn, enIn, typeIn, tcAddr, enOut, typeOut);
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input entypeEn, enIn;
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input entypeEn, enIn;
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input [`tcTypeLen-1:0] typeIn; // could be `counterTypeLen
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input [`tcTypeLen-1:0] typeIn; // could be `counterTypeLen
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input [`tcAddrLen-1:0] tcAddr;
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input [`tcAddrLen-1:0] tcAddr;
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output wire [`tcNumbers-1:0] enOut;
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output wire [`tcNumbers-1:0] enOut;
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output wire [(`tcNumbers*`tcTypeLen)-1:0] typeOut;
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output wire [(`tcNumbers*`tcTypeLen)-1:0] typeOut;
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reg enables [`tcNumbers-1:0];
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reg enables [`tcNumbers-1:0];
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reg [`tcTypeLen-1:0] types [`tcNumbers-1:0];
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reg [`tcTypeLen-1:0] types [`tcNumbers-1:0];
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always @ *
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always @ *
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begin
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begin
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if (entypeEn)
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if (entypeEn)
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begin
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begin
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enables[tcAddr] = enIn;
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enables[tcAddr] = enIn;
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types[tcAddr] = typeIn;
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types[tcAddr] = typeIn;
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end
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end
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end
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end
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// assign outputs . . .
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// assign outputs . . .
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// can write generic???
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// can write generic???
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assign enOut[0]= enables[0];
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assign enOut[0]= enables[0];
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assign enOut[1]= enables[1];
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assign enOut[1]= enables[1];
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assign enOut[2]= enables[2];
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assign enOut[2]= enables[2];
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assign enOut[3]= enables[3];
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assign enOut[3]= enables[3];
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assign enOut[4]= enables[4];
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assign enOut[4]= enables[4];
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assign enOut[5]= enables[5];
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assign enOut[5]= enables[5];
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assign enOut[6]= enables[6];
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assign enOut[6]= enables[6];
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assign enOut[7]= enables[7];
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assign enOut[7]= enables[7];
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assign typeOut[`tcTypeLen-1:0] = types[0];
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assign typeOut[`tcTypeLen-1:0] = types[0];
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assign typeOut[(`tcTypeLen*2)-1:`tcTypeLen] = types[1];
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assign typeOut[(`tcTypeLen*2)-1:`tcTypeLen] = types[1];
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assign typeOut[(`tcTypeLen*3)-1:(`tcTypeLen*2)] = types[2];
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assign typeOut[(`tcTypeLen*3)-1:(`tcTypeLen*2)] = types[2];
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assign typeOut[(`tcTypeLen*4)-1:(`tcTypeLen*3)] = types[3];
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assign typeOut[(`tcTypeLen*4)-1:(`tcTypeLen*3)] = types[3];
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assign typeOut[(`tcTypeLen*5)-1:(`tcTypeLen*4)] = types[4];
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assign typeOut[(`tcTypeLen*5)-1:(`tcTypeLen*4)] = types[4];
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assign typeOut[(`tcTypeLen*6)-1:(`tcTypeLen*5)] = types[5];
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assign typeOut[(`tcTypeLen*6)-1:(`tcTypeLen*5)] = types[5];
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assign typeOut[(`tcTypeLen*7)-1:(`tcTypeLen*6)] = types[6];
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assign typeOut[(`tcTypeLen*7)-1:(`tcTypeLen*6)] = types[6];
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assign typeOut[(`tcTypeLen*8)-1:(`tcTypeLen*7)] = types[7];
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assign typeOut[(`tcTypeLen*8)-1:(`tcTypeLen*7)] = types[7];
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endmodule
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endmodule
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