`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module top(clk, reset, IN, OUT
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module top(clk, reset, IN, OUT
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, rx, tx
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, rx, tx
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, MISO, MOSI, SCK
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, MISO, MOSI, SCK
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`endif
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`endif
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);
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);
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input clk,reset;
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input clk,reset;
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input [`inputNumber-1:0] IN;
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input [`inputNumber-1:0] IN;
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output [`outputNumber-1:0] OUT;
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output [`outputNumber-1:0] OUT;
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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input rx;
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input rx;
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output tx;
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output tx;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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input MISO;
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input MISO;
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output MOSI, SCK;
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output MOSI, SCK;
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`endif
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`endif
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// wires (interconnects) of execution unit
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// wires (interconnects) of execution unit
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wire [`instLen-1:0] pcOut;
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wire [`instLen-1:0] pcOut;
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wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
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wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
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wire [`instOpCodeLen-1:0] instOpCode;
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wire [`instOpCodeLen-1:0] instOpCode;
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wire [`instFieldLen-1:0] instField;
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wire [`instFieldLen-1:0] instField;
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wire [7:0] accMuxOut;
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wire [7:0] accMuxOut;
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wire [7:0] accOut;
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wire [7:0] accOut;
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wire [7:0] op2MuxOut;
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wire [7:0] op2MuxOut;
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wire [7:0] aluOut;
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wire [7:0] aluOut;
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wire bitNegatorRamOut, bitOut;
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wire bitNegatorRamOut, bitOut;
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wire [7:0] byteNegatorRamOut, byteOut;
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wire [7:0] byteNegatorRamOut, byteOut;
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wire inputReadOutData, outputReadOut;
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wire inputReadOutData, outputReadOut;
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wire branchOutc;
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wire branchOutc;
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wire [`accMuxSelLen-1:0] accMuxSelOutc;
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wire [`accMuxSelLen-1:0] accMuxSelOutc;
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wire accEnOutc;
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wire accEnOutc;
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wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
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wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
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wire aluEnc;
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wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
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wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
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wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
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wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
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wire inputReadOutc, outputRwOutc;
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wire inputReadOutc, outputRwOutc;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
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wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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wire uartReadOutc, uartWriteOutc;
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wire uartReadOutc, uartWriteOutc;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
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wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
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`endif
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`endif
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wire branchOut;
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wire branchOut;
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wire [`accMuxSelLen-1:0] accMuxSelOut;
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wire [`accMuxSelLen-1:0] accMuxSelOut;
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wire accEnOut;
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wire accEnOut;
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wire [`op2MuxSelLen-1:0] op2MuxSelOut;
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wire [`op2MuxSelLen-1:0] op2MuxSelOut;
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wire aluEn;
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wire [`aluOpcodeLen-1:0] aluOpcodeOut;
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wire [`aluOpcodeLen-1:0] aluOpcodeOut;
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wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
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wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
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wire inputReadOut, outputRwOut;
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wire inputReadOut, outputRwOut;
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
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wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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wire uartReadOut, uartWriteOut;
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wire uartReadOut, uartWriteOut;
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
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wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
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`endif
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`endif
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// wires (interconnects) of timer & counter
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// wires (interconnects) of timer & counter
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
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wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
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wire [7:0] tcAccumOut;
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wire [7:0] tcAccumOut;
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wire [7:0] tcLoadOut;
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wire [7:0] tcLoadOut;
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wire [`tcNumbers-1:0] enWires;
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wire [`tcNumbers-1:0] enWires;
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wire [`tcNumbers-1:0] resetWires;
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wire [`tcNumbers-1:0] resetWires;
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wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
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wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
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wire [(`tcNumbers*2)-1:0] typeWires;
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wire [(`tcNumbers*2)-1:0] typeWires;
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wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
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wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
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`endif
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`endif
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// wires (interconnects) of UART
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// wires (interconnects) of UART
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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`endif
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`endif
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// wires (interconnects) of SPI
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// wires (interconnects) of SPI
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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`endif
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`endif
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//-------- Fetch Unit Module Instances
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//-------- Fetch Unit Module Instances
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// all necessary
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// all necessary
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pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
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pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
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// instruction ROM is declared using xilinx primitive
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// instruction ROM is declared using xilinx primitive
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RAMB16_S18 rom ( .DI(),
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RAMB16_S18 rom ( .DI(),
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.DIP(),
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.DIP(),
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.ADDR(pcOut),
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.ADDR(pcOut),
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.EN(1'b1),
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.EN(1'b1),
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.WE(),
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.WE(),
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.SSR(1'b0),
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.SSR(1'b0),
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.CLK(clk),
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.CLK(clk),
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.DO(romOut),
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.DO(romOut),
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.DOP());
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.DOP());
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instReg IntructionRegister (romOut, instOpCode, instField);
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instReg IntructionRegister (romOut, instOpCode, instField);
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// pipeline register
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// pipeline register
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wire [`instOpCodeLen-1:0] instOpCode1;
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wire [`instOpCodeLen-1:0] instOpCode1;
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wire [`instFieldLen-1:0] instField1;
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wire [`instFieldLen-1:0] instField1;
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wire [`instFieldLen-1:0] instField2;
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wire [`instFieldLen-1:0] instField2;
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ppReg1 PipeLine_Reg1 (clk, instOpcode, instField, instOpcode1, instField1);
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ppReg1 PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);
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//-------- Control Unit Module Instance
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//-------- Control Unit Module Instance
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controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
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controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
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branchc,
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branchOutc,
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accMuxSelc, accEnc, op2MuxSelc, aluOpcodec,
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accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
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bitRamEnc, bitRamRwc, byteRamEnc, byteRamRwc,
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bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
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inputReadc, outputRwc
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, entypeEnc, tcAccReadc, tcResetEnc, tcPresetEnc, tcLoadEnc
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, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartReadc, uartWritec
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, uartReadOutc, uartWriteOutcc
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, sconEnc, spiStatReadc, spiBufReadc, spiBufWritec, spiBufShiftc
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, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
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`endif
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`endif
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);
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);
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// pipeline register
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// pipeline register
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ppReg2 PipeLine_Reg2 (clk,
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ppReg2 PipeLine_Reg2 (clk,
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branchOutc,
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branchOutc,
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accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluOpcodeOutc, bitRamEnOutc,
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accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
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bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
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bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
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, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartReadOutc, uartWriteOutcc
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, uartReadOutc, uartWriteOutcc
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
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, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
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`endif
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`endif
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, instField1
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, instField1
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, branchOut,
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, branchOut,
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accMuxSelOut, accEnOut, op2MuxSelOut, aluOpcodeOut,
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accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
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bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
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bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
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inputReadOut, outputRwOut
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inputReadOut, outputRwOut
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
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, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartReadOut, uartWriteOut
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, uartReadOut, uartWriteOut
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
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, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
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`endif
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`endif
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, instField2
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, instField2
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);
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);
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//-------- Execute Unit Modules Instances
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//-------- Execute Unit Modules Instances
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// all necessary
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// all necessary
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accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut
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accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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, tcLoadOut, tcAccOut
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, tcLoadOut, tcAccOut
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`endif
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`endif
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`ifdef UART_peripheral
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`ifdef UART_peripheral
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, uartDataOut
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, uartDataOut
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`endif
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`endif
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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, spiStatOut, spiBufOut
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, spiStatOut, spiBufOut
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`endif
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`endif
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, accMuxOut
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, accMuxOut
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);
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);
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accumulator acc (accMuxOut, accEnOut, accOut);
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accumulator acc (accMuxOut, accEnOut, accOut);
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op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
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op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
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wire [7:0] op2Out;
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wire [7:0] op2Out;
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byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
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byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
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alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluOut, carryOut);
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alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
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wire bitIn;
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wire bitIn;
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bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);
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bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);
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bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
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bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
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wire [7:0] byteIn;
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wire [7:0] byteIn;
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byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);
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byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);
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byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
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byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
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inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
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inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
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outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
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outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
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//---------- Timer & Counter Modules
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//---------- Timer & Counter Modules
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// optional
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// optional
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`ifdef timerAndCounter_peripheral
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`ifdef timerAndCounter_peripheral
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tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
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tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
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tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
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tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
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tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
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tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
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tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
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tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
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tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
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tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
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timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
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timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
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timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
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timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
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timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
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timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
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timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
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timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
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counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
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counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
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counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
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counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
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counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
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counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
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counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
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counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
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`endif
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`endif
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//---------- UART Modules
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//---------- UART Modules
|
// optional
|
// optional
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|
|
`ifdef UART_peripheral
|
`ifdef UART_peripheral
|
|
|
wire brgOut;
|
wire brgOut;
|
wire txDoneTick, txStart;
|
wire txDoneTick, txStart;
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wire rxDoneTick;
|
wire rxDoneTick;
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wire [7:0] recFifoData, transFifoData;
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wire [7:0] recFifoData, transFifoData;
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|
|
|
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uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
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uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
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uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
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uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
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uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
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uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
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uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
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uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
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uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
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uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
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`endif
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`endif
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//---------- SPI Modules
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//---------- SPI Modules
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// optional
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// optional
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`ifdef SPI_peripheral
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`ifdef SPI_peripheral
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spiStatReg SPI_STATUS_REG ();
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spiConReg SPI_CONTROL_REG ();
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spiBufReg SPI_BUFFER_REG ();
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spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
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spiEngine SPI_MAIN ();
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`endif
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`endif
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endmodule
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endmodule
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