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--////////////////////////////////////////////////////////////////////////////////////////////////
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--//// ////
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--//// ////
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--//// This file is part of the project ////
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--//// "instruction_list_pipelined_processor_with_peripherals" ////
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--//// ////
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--//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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--//// ////
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--//// ////
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--//// Author: ////
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--//// - Mahesh Sukhdeo Palve ////
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--//// ////
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--////////////////////////////////////////////////////////////////////////////////////////////////
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--////////////////////////////////////////////////////////////////////////////////////////////////
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--//// ////
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--//// ////
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--//// ////
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--//// This source file may be used and distributed without ////
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--//// restriction provided that this copyright statement is not ////
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--//// removed from the file and that any derivative work contains ////
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--//// the original copyright notice and the associated disclaimer. ////
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--//// ////
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--//// This source file is free software; you can redistribute it ////
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--//// and/or modify it under the terms of the GNU Lesser General ////
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--//// Public License as published by the Free Software Foundation; ////
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--//// either version 2.1 of the License, or (at your option) any ////
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--//// later version. ////
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--//// ////
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--//// This source is distributed in the hope that it will be ////
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--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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--//// PURPOSE. See the GNU Lesser General Public License for more ////
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--//// details. ////
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--//// ////
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--//// You should have received a copy of the GNU Lesser General ////
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--//// Public License along with this source; if not, download it ////
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--//// from http://www.opencores.org/lgpl.shtml ////
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--//// ////
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--////////////////////////////////////////////////////////////////////////////////////////////////
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.math_real.all;
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use IEEE.math_real.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity uartBrg is
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entity uartBrg is
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generic (
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generic (
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DIVISOR: natural := 32000000/(16*9600) -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
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DIVISOR: natural := 32000000/(16*9600) -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
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-- 2400 -> 2604
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-- 2400 -> 2604
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-- 9600 -> 651
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-- 9600 -> 651
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-- 115200 -> 54
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-- 115200 -> 54
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-- 1562500 -> 4
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-- 1562500 -> 4
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-- 2083333 -> 3
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-- 2083333 -> 3
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);
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);
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port (
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port (
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clk: in std_logic; -- clock
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clk: in std_logic; -- clock
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reset: in std_logic; -- reset
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reset: in std_logic; -- reset
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outp : out std_logic
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outp : out std_logic
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);
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);
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end uartBrg;
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end uartBrg;
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architecture Behavioral of uartBrg is
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architecture Behavioral of uartBrg is
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constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
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constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
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signal sample: std_logic; -- 1 clk spike at 16x baud rate
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signal sample: std_logic; -- 1 clk spike at 16x baud rate
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signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0) := (others=> '0'); -- should fit values in 0..DIVISOR-1
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signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0) := (others=> '0'); -- should fit values in 0..DIVISOR-1
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begin
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begin
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-- sample signal at 16x baud rate, 1 CLK spikes
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-- sample signal at 16x baud rate, 1 CLK spikes
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sample_process: process (clk,reset) is
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sample_process: process (clk,reset) is
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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sample_counter <= (others => '0');
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sample_counter <= (others => '0');
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sample <= '0';
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sample <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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if sample_counter = DIVISOR-1 then
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if sample_counter = DIVISOR-1 then
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sample <= '1';
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sample <= '1';
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sample_counter <= (others => '0');
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sample_counter <= (others => '0');
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else
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else
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sample <= '0';
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sample <= '0';
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sample_counter <= sample_counter + 1;
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sample_counter <= sample_counter + 1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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outp <= sample;
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outp <= sample;
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