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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// This file is part of the project ////
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//// "instruction_list_pipelined_processor_with_peripherals" ////
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//// ////
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//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////
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//// ////
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//// ////
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//// Author: ////
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//// - Mahesh Sukhdeo Palve ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "defines.v"
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`include "defines.v"
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module uartTrans (clk, reset, sTick, txDoneTick, din, tx, txStart);
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module uartTrans (clk, reset, sTick, txDoneTick, din, tx, txStart);
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parameter dataBits = `dataBits;
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parameter dataBits = `dataBits;
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parameter sbTick = `sbTick;
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parameter sbTick = `sbTick;
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input [dataBits-1 :0] din;
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input [dataBits-1 :0] din;
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input clk, reset, sTick, txStart;
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input clk, reset, sTick, txStart;
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output tx, txDoneTick;
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output tx, txDoneTick;
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reg txDoneTick;
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reg txDoneTick;
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/*
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/*
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should be impleneted as a 4-state FSM : idle, start, data, stop;
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should be impleneted as a 4-state FSM : idle, start, data, stop;
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*/
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*/
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localparam [1:0] idle = 2'b00, start = 2'b01, data = 2'b10, stop = 2'b11;
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localparam [1:0] idle = 2'b00, start = 2'b01, data = 2'b10, stop = 2'b11;
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reg [1:0] stateReg, stateNext; // current and next states
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reg [1:0] stateReg, stateNext; // current and next states
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reg [3:0] sReg, sNext; // counter
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reg [3:0] sReg, sNext; // counter
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reg [2:0] nReg, nNext; // counter
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reg [2:0] nReg, nNext; // counter
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reg [7:0] bReg, bNext; // perhaps keeps data to be sent
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reg [7:0] bReg, bNext; // perhaps keeps data to be sent
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reg txReg, txNext; // current bit being transferred
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reg txReg, txNext; // current bit being transferred
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// reset and non-reset conditions:
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// reset and non-reset conditions:
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always @ (posedge clk or posedge reset)
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always @ (posedge clk or posedge reset)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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stateReg <= idle;
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stateReg <= idle;
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sReg <= 1'b0;
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sReg <= 1'b0;
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bReg <= 1'b0;
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bReg <= 1'b0;
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nReg <= 1'b0;
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nReg <= 1'b0;
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txReg <= 1'b1;
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txReg <= 1'b1;
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end // end if
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end // end if
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else
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else
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begin
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begin
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stateReg <= stateNext;
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stateReg <= stateNext;
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sReg <= sNext;
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sReg <= sNext;
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bReg <= bNext;
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bReg <= bNext;
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nReg <= nNext;
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nReg <= nNext;
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txReg <= txNext;
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txReg <= txNext;
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end // end else
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end // end else
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end // end always
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end // end always
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// FSM:
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// FSM:
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always @ *
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always @ *
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begin
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begin
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stateNext = stateReg;
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stateNext = stateReg;
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sNext = sReg;
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sNext = sReg;
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bNext = bReg;
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bNext = bReg;
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nNext = nReg;
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nNext = nReg;
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txNext = txReg;
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txNext = txReg;
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txDoneTick = 1'b0; // not done yet!
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txDoneTick = 1'b0; // not done yet!
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case (stateReg)
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case (stateReg)
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idle : begin
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idle : begin
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txNext = 1'b1; // start bit '0'; thus, send '1' in idle
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txNext = 1'b1; // start bit '0'; thus, send '1' in idle
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if (txStart)
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if (txStart)
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begin
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begin
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txDoneTick = 1'b1; // generate rd for fifo **
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txDoneTick = 1'b1; // generate rd for fifo **
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stateNext = start; // should go into start state
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stateNext = start; // should go into start state
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sNext = 0;
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sNext = 0;
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end // end if txStart
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end // end if txStart
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// in idle state unless txStart...
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// in idle state unless txStart...
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end // end idle case
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end // end idle case
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start : begin
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start : begin
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txNext = 0;
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txNext = 0;
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txDoneTick = 1'b0; // **
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txDoneTick = 1'b0; // **
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bNext = din; // take din into bReg
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bNext = din; // take din into bReg
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if (sTick)
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if (sTick)
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if (sReg == 15)
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if (sReg == 15)
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begin
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begin
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stateNext = data;
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stateNext = data;
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sNext = 1'b0;
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sNext = 1'b0;
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nNext = 1'b0;
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nNext = 1'b0;
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end // end if sReg==15
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end // end if sReg==15
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else
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else
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sNext = sReg + 1; // keep incrementing sNext (sReg)
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sNext = sReg + 1; // keep incrementing sNext (sReg)
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// sReg = sNext on each clk edge !!
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// sReg = sNext on each clk edge !!
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end // end start case
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end // end start case
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data : begin
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data : begin
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txNext = bReg[0]; // keep sending LSB of bReg
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txNext = bReg[0]; // keep sending LSB of bReg
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if (sTick)
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if (sTick)
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if (sReg == 15)
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if (sReg == 15)
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begin
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begin
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sNext = 0; // reset counter
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sNext = 0; // reset counter
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bNext = bReg >> 1; // shift word to be sent
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bNext = bReg >> 1; // shift word to be sent
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if (nReg == (dataBits-1))
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if (nReg == (dataBits-1))
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stateNext = stop;
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stateNext = stop;
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else
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else
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nNext = nReg +1;
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nNext = nReg +1;
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end // end if sReg==15
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end // end if sReg==15
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else
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else
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sNext = sReg + 1;
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sNext = sReg + 1;
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end // end data state
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end // end data state
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stop : begin
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stop : begin
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txNext = 1'b1;
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txNext = 1'b1;
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if (sTick)
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if (sTick)
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if (sReg == sbTick-1)
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if (sReg == sbTick-1)
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begin
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begin
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stateNext = idle;
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stateNext = idle;
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//txDoneTick = 1'b1; it's working as read signal to
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//txDoneTick = 1'b1; it's working as read signal to
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// fifo, so, used at starting . . .
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// fifo, so, used at starting . . .
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end //end if sReg==15
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end //end if sReg==15
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else
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else
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sNext = sReg + 1;
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sNext = sReg + 1;
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end // end stop state
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end // end stop state
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endcase
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endcase
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end // end always combinatorial
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end // end always combinatorial
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// output bit-stream
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// output bit-stream
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assign tx = txReg;
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assign tx = txReg;
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endmodule
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endmodule
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