# programmer for 8-bit pipelined processor
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# programmer for 8-bit pipelined processor
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# Mahesh Sukhdeo Palve
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# Mahesh Sukhdeo Palve
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# 09042014
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# 09042014
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# !/usr/bin/perl
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# !/usr/bin/perl
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use warnings;
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use warnings;
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# use strict;
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# use strict;
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my $file_asm = '> C:\asm.txt';
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my $file_asm = '> C:\asm.txt';
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open FILE_ASM, $file_asm or die " PROBLEM READING FILE : $! \n";
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open FILE_ASM, $file_asm or die " PROBLEM READING FILE : $! \n";
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my $file_rom = '> C:\rom.v';
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my $file_rom = '> C:\rom.v';
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open FILE_V, $file_rom or die "PROBLEM READING FILE : $! \n";
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open FILE_V, $file_rom or die "PROBLEM READING FILE : $! \n";
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print ("\n\nLast modified by : Mahesh Sukhdeo Palve");
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print ("\n\nLast modified by : Mahesh Sukhdeo Palve");
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print (" \n\n8-bit Pipeline Processor");
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print (" \n\n8-bit Pipeline Processor");
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print (" \n\n for Open Cores (opencores.org)");
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print (" \n\n for Open Cores (opencores.org)");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n\t\tPROGRAMMER . . .\n\n");
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print ("\n\n\t\tPROGRAMMER . . .\n\n");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\n\n------------------------------------------------");
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print ("\nStart entering instructions-\n");
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print ("\nStart entering instructions-\n");
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# take instruction?
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# take instruction?
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my $inst = 0;
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my $inst = 0;
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my $addr = 0;
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my $addr = 0;
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print FILE_V "`include \"defines.v\"\n`include \"timescale.v\"\n\n";
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print FILE_V "`include \"defines.v\"\n`include \"timescale.v\"\n\n";
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print FILE_V "\tmodule\trom (clk, addr, code);\n";
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print FILE_V "\tmodule\trom (clk, addr, code);\n";
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print FILE_V "\t\tinput clk;\n\t\tinput [`instAddrLen-1:0] addr; \n\t\t output [`instLen-1:0] code;\n\n";
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print FILE_V "\t\tinput clk;\n\t\tinput [`instAddrLen-1:0] addr; \n\t\t output [`instLen-1:0] code;\n\n";
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print FILE_V "\t\treg [`instLen-1:0] code;";
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print FILE_V "\t\treg [`instLen-1:0] code;";
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print FILE_V "\n\n\n\t\t\talways @ (posedge clk)\n\t\t\tbegin\n\n";
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print FILE_V "\n\n\n\t\t\talways @ (posedge clk)\n\t\t\tbegin\n\n";
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print FILE_V "\t\t\t case (addr)";
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print FILE_V "\t\t\t case (addr)";
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while ($inst ne END)
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while ($inst ne END)
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{
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{
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print "\nmnemonic :\t";
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print "\nmnemonic :\t";
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$inst = ;
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$inst = ;
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chop ($inst);
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chop ($inst);
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my $opcode = getOpcode($inst);
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my $opcode = getOpcode($inst);
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# print "\nopcode for $inst is $opcode\n";
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# print "\nopcode for $inst is $opcode\n";
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my $field = getField($inst);
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my $field = getField($inst);
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# print "\nfield for $inst is $field\n";
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# print "\nfield for $inst is $field\n";
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my $instruction = $opcode.$field;
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my $instruction = $opcode.$field;
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print "\n The instruction at address $addr is $instruction\n\n";
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print "\n The instruction at address $addr is $instruction\n\n";
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my $zero = 0;
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my $zero = 0;
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print FILE_ASM $inst."\t\t".$field."\n";
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print FILE_ASM $inst."\t\t".$field."\n";
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print FILE_V "\n\t\t\t\t$addr\t:\tcode = 15'b$instruction;";
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print FILE_V "\n\t\t\t\t$addr\t:\tcode = 15'b$instruction;";
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$addr = $addr + 1;
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$addr = $addr + 1;
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}
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}
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print FILE_V "\n\n\t\t\tdefault\t:\tcode = 15'b111111111111111;";
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print FILE_V "\n\n\t\t\tdefault\t:\tcode = 15'b111111111111111;";
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print FILE_V "\n\t\tendcase\nend\n\nendmodule\n";
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print FILE_V "\n\t\tendcase\nend\n\nendmodule\n";
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sub bin2hex {
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my $bin = shift;
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# Make input bit string a multiple of 4
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#$bin = substr("0000",length($bin)%4) . $bin if length($bin)%4;
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my ($hex, $nybble) = ("");
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while (length($bin)) {
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($nybble,$bin) = (substr($bin,0,4), substr($bin,4)); # (substr($bin,0,4), substr($bin,4));
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#substr extracts a substring . . .
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$nybble = eval "0b$nybble";
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$hex .= substr("0123456789ABCDEF", $nybble, 1);
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}
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return $hex;
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}
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##############
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##############
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# getOpcode
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# getOpcode
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sub getOpcode{
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sub getOpcode{
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my $temp;
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my $temp;
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my $zero = 0;
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my $zero = 0;
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my $opcod;
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my $opcod;
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use Switch;
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use Switch;
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switch ($inst) {
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switch ($inst) {
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case END { $temp = 0; $opcod = $temp.$temp.$temp.$temp.$temp;};
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case END { $temp = 0; $opcod = $temp.$temp.$temp.$temp.$temp;};
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case JMP { $temp = 1; $opcod = $zero.$zero.$zero.$zero.$temp;};
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case JMP { $temp = 1; $opcod = $zero.$zero.$zero.$zero.$temp;};
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case Ld { $temp = 10; $opcod = $zero.$zero.$zero.$temp;};
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case Ld { $temp = 10; $opcod = $zero.$zero.$zero.$temp;};
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case Ldi { $temp = 11; $opcod = $zero.$zero.$zero.$temp;};
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case Ldi { $temp = 11; $opcod = $zero.$zero.$zero.$temp;};
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case ST { $temp = 100; $opcod = $zero.$zero.$temp;};
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case ST { $temp = 100; $opcod = $zero.$zero.$temp;};
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case ADD { $temp = 101; $opcod = $zero.$zero.$temp;};
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case ADD { $temp = 101; $opcod = $zero.$zero.$temp;};
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case SUB { $temp = 110; $opcod = $zero.$zero.$temp;};
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case SUB { $temp = 110; $opcod = $zero.$zero.$temp;};
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case MUL { $temp = 111; $opcod = $zero.$zero.$temp;};
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case MUL { $temp = 111; $opcod = $zero.$zero.$temp;};
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case DIV { $temp = 1000; $opcod = $zero.$temp;};
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case DIV { $temp = 1000; $opcod = $zero.$temp;};
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case AND { $temp = 1001; $opcod = $zero.$temp;};
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case AND { $temp = 1001; $opcod = $zero.$temp;};
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case OR { $temp = 1010; $opcod = $zero.$temp;};
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case OR { $temp = 1010; $opcod = $zero.$temp;};
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case XOR { $temp = 1011; $opcod = $zero.$temp;};
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case XOR { $temp = 1011; $opcod = $zero.$temp;};
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case GT { $temp = 1100; $opcod = $zero.$temp;};
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case GT { $temp = 1100; $opcod = $zero.$temp;};
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case GE { $temp = 1101; $opcod = $zero.$temp;};
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case GE { $temp = 1101; $opcod = $zero.$temp;};
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case EQ { $temp = 1110; $opcod = $zero.$temp;};
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case EQ { $temp = 1110; $opcod = $zero.$temp;};
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case LE { $temp = 1111; $opcod = $zero.$temp;};
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case LE { $temp = 1111; $opcod = $zero.$temp;};
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case LT { $opcod = 10000;};
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case LT { $opcod = 10000;};
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case PRE { $opcod = 10001;};
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case PRE { $opcod = 10001;};
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case ETY { $opcod = 10010;};
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case ETY { $opcod = 10010;};
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case RST { $opcod = 10011;};
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case RST { $opcod = 10011;};
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case LdTC { $opcod = 10100;};
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case LdTC { $opcod = 10100;};
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case LdACC { $opcod = 10101;};
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case LdACC { $opcod = 10101;};
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case UARTrd { $opcod = 10110;};
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case UARTrd { $opcod = 10110;};
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case UARTwr { $opcod = 10111;};
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case UARTwr { $opcod = 10111;};
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case UARTstat { $opcod = 11000;};
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case UARTstat { $opcod = 11000;};
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case SPIxFER { $opcod = 11001;};
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case SPIxFER { $opcod = 11001;};
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case SPIstat { $opcod = 11010;};
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case SPIstat { $opcod = 11010;};
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case SPIwBUF { $opcod = 11011;};
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case SPIwBUF { $opcod = 11011;};
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case SPIrBUF { $opcod = 11100;}
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case SPIrBUF { $opcod = 11100;}
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else {print " Inserted NOP!"; $opcod = 11111;};
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else {print " Inserted NOP!"; $opcod = 11111;};
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}
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}
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return $opcod;
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return $opcod;
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}
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}
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##################
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##################
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# getField
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# getField
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sub getField{
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sub getField{
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my $fld = 0;
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my $fld = 0;
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use Switch;
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use Switch;
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my $zero = 0;
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my $zero = 0;
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my $tmp;
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my $tmp;
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my $response = 0;
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my $response = 0;
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my $negate = 0;
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my $negate = 0;
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my $iomem = 0;
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my $iomem = 0;
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my $iomemaddr = 0;
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my $iomemaddr = 0;
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switch ($inst){
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switch ($inst){
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case END{
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case END{
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print "\nis start address 0? Y or N\t";
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print "\nis start address 0? Y or N\t";
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$response = ; chop($response);
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$response = ; chop($response);
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if ($response eq Y){
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if ($response eq Y){
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$tmp = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$tmp = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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}
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}
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else{
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else{
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print "\nstart address (10 bit) :\t";
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print "\nstart address (10 bit) :\t";
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$tmp = ;
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$tmp = ;
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chop($tmp);
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chop($tmp);
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}
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}
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$fld = $tmp;
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$fld = $tmp;
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};
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};
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case JMP {
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case JMP {
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print "\n Jump to address :\t";
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print "\n Jump to address :\t";
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$fld = ;
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$fld = ;
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chop($fld);
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chop($fld);
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};
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};
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case Ld {
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case Ld {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case Ldi {
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case Ldi {
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print "\nImmediate Data (8-bit):\t";
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print "\nImmediate Data (8-bit):\t";
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$temp = ; chop($temp);
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$temp = ; chop($temp);
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$fld = $zero.$zero.$temp;
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$fld = $zero.$zero.$temp;
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}
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}
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case ST {
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case ST {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case ADD {
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case ADD {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case SUB {
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case SUB {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case MUL {
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case MUL {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case DIV {
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case DIV {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case AND {
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case AND {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case OR {
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case OR {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case XOR {
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case XOR {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case GT {
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case GT {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case GE {
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case GE {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case EQ {
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case EQ {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case LE {
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case LE {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case LT {
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case LT {
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$fld = sub1();
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$fld = sub1();
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};
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};
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case PRE {
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case PRE {
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my $addr = sub2(); my $zero = 0;
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my $addr = sub2(); my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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};
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};
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case ETY {
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case ETY {
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print "\nAssert (1) or De-assert (0) enable signal?\t";
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print "\nAssert (1) or De-assert (0) enable signal?\t";
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my $resp = ; chop($resp);
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my $resp = ; chop($resp);
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print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t";
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print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t";
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my $resp2 = ; chop($resp2);
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my $resp2 = ; chop($resp2);
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my $addr = sub2(); my $zero = 0;
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my $addr = sub2(); my $zero = 0;
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$fld = $zero.$zero.$zero.$resp.$resp2.$addr;
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$fld = $zero.$zero.$zero.$resp.$resp2.$addr;
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};
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};
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case RST {
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case RST {
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print "\nAssert (1) or De-assert (0) Reset signal?\t";
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print "\nAssert (1) or De-assert (0) Reset signal?\t";
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my $resp = ; chop($resp);
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my $resp = ; chop($resp);
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my $zero = 0;
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my $zero = 0;
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my $addr = sub2();
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my $addr = sub2();
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$fld = $zero.$zero.$zero.$zero.$zero.$resp.$addr;
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$fld = $zero.$zero.$zero.$zero.$zero.$resp.$addr;
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};
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};
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case LdTC {
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case LdTC {
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my $addr = sub2(); my $zero = 0;
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my $addr = sub2(); my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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};
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};
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case LdACC {
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case LdACC {
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my $addr = sub2(); my $zero = 0;
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my $addr = sub2(); my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
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};
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};
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case UARTrd {
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case UARTrd {
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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};
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};
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case UARTwr {
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case UARTwr {
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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};
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};
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case UARTstat{
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case UARTstat{
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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};
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};
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case SPIxFER{
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case SPIxFER{
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print "\nEnable (1) or disable (0)?\t";
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print "\nEnable (1) or disable (0)?\t";
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my $resp = ; chop($resp);
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my $resp = ; chop($resp);
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print "\nShift (1) or Stop shift (0)?\t";
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print "\nShift (1) or Stop shift (0)?\t";
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my $resp2 = ; chop($resp2);
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my $resp2 = ; chop($resp2);
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$resp.$zero.$zero.$zero.$zero.$zero.$zero.$resp2;
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$fld = $zero.$zero.$resp.$zero.$zero.$zero.$zero.$zero.$zero.$resp2;
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}
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}
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case SPIstat{
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case SPIstat{
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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};
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};
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case SPIrBUF{
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case SPIrBUF{
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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};
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};
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case SPIwBUF{
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case SPIwBUF{
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my $zero = 0;
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my $zero = 0;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
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}
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}
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else {
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else {
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$fld = 1111111111;
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$fld = 1111111111;
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};
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};
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}
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}
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return $fld;
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return $fld;
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}
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}
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sub sub1{
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sub sub1{
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print "\nNegate? Y or N\t";
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print "\nNegate? Y or N\t";
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$response = ; chop($response);
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$response = ; chop($response);
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if ($response eq Y){ $negate = 1;}
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if ($response eq Y){ $negate = 1;}
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else {$negate = 0};
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else {$negate = 0};
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print "\nInput (i) / Output (o) / bitRAM (b) / ByteRAM (B)?";
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print "\nInput (i) / Output (o) / bitRAM (b) / ByteRAM (B)?";
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my $select = ; chop($select);
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my $select = ; chop($select);
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if ($select eq i){
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if ($select eq i){
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my $zero = 0; $iomem = $zero.$zero;
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my $zero = 0; $iomem = $zero.$zero;
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print "\ninput address :\t";
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print "\ninput address :\t";
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$iomemaddr = ; chop($iomemaddr);
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$iomemaddr = ; chop($iomemaddr);
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}
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}
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if ($select eq o){
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if ($select eq o){
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$temp = 1; $zero = 0;
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$temp = 1; $zero = 0;
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$iomem = $zero.$temp;
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$iomem = $zero.$temp;
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print "\noutput address :\t";
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print "\noutput address :\t";
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$iomemaddr = ; chop($iomemaddr);
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$iomemaddr = ; chop($iomemaddr);
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}
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}
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if ($select eq b){
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if ($select eq b){
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$iomem = 10;
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$iomem = 10;
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print "\nbit RAM address :\t";
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print "\nbit RAM address :\t";
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$iomemaddr = ; chop($iomemaddr);
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$iomemaddr = ; chop($iomemaddr);
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}
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}
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if ($select eq B){
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if ($select eq B){
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$iomem = 11;
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$iomem = 11;
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print "\nByte RAM address :\t";
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print "\nByte RAM address :\t";
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$iomemaddr = ; chop($iomemaddr);
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$iomemaddr = ; chop($iomemaddr);
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}
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}
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$fld = $negate.$iomem.$iomemaddr;
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$fld = $negate.$iomem.$iomemaddr;
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return $fld;
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return $fld;
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}
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}
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sub sub2 {
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sub sub2 {
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print "\nEnter Timer/Counter Address (4-bit):\t";
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print "\nEnter Timer/Counter Address (4-bit):\t";
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my $addrs = ;
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my $addrs = ;
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chop ($addrs);
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chop ($addrs);
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return $addrs;
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return $addrs;
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