""" xcxcxc
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"""
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Builds VHDL file from a template by replacing tags with parameter values.
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See the makefiles of the code samples included in project ION for usage
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examples.
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"""
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"""
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import sys
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import sys
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import getopt
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import getopt
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import math
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import math
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def usage():
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def usage():
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print ""
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print ""
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print "usage:"
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print "usage:"
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print "python bin2hdl.py [arguments]\n"
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print "python bin2hdl.py [arguments]\n"
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print "Inserts data in VHDL template\n"
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print "Inserts data in VHDL template\n"
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print "ALL of the following arguments should be given, in any order:"
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print "ALL of the following arguments should be given, in any order:"
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print "{c|code} <filename> Code binary image file name"
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print "{c|code} <filename> Code binary image file name"
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print "{v|vhdl} <filename> VHDL template"
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print "{v|vhdl} <filename> VHDL template"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{a|architecture} <name> Name of target VHDL architecture"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{e|entity} <name> Name of target VHDL entity"
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print "{o|output} <filename> Target VHDL file name"
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print "{o|output} <filename> Target VHDL file name"
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print "code_size <number> Size of bram memory in words (decimal)"
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print "code_size <number> Size of bram memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "data_size <number> Size of data memory in words (decimal)"
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print "flash_size <number> Size of flash memory in words (decimal)"
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print "flash_size <number> Size of flash memory in words (decimal)"
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print "(note the flash and xram info are used in simulation only)"
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print "(note the flash and xram info are used in simulation only)"
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print ""
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print ""
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print "Additionally, any of these arguments can be given:"
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print "Additionally, any of these arguments can be given:"
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print "{t|log_trigger} <number> Fetch address that triggers file logging"
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print "{t|log_trigger} <number> Fetch address that triggers file logging"
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print "{s|sim_len} <number> Length of simulation in clock cycles"
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print "{s|sim_len} <number> Length of simulation in clock cycles"
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print "{d|data} <filename> Data binary image file name or 'empty'"
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print "{d|data} <filename> Data binary image file name or 'empty'"
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print "{h|help} Display some help text and exit"
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print "{h|help} Display some help text and exit"
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print "{i|indent} <number> Indentation in VHDL tables (decimal)"
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print "{i|indent} <number> Indentation in VHDL tables (decimal)"
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def help():
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def help():
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print "\nPurpose:\n"
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print "\nPurpose:\n"
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print "Reads the code and data binary files and 'slices' them in byte"
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print "Reads the code and data binary files and 'slices' them in byte"
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print "columns."
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print "columns."
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print "The data columns are converted to VHDL strings and then inserted"
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print "The data columns are converted to VHDL strings and then inserted"
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print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
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print "into the vhdl template, in place of tags @code0@ .. @code3@ and "
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print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
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print "@data0@ .. @data3@. Column 0 is LSB and column3 is MSB.\n"
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print "Tags like @data31@ and @data20@ etc. can be used to initialize"
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print "Tags like @data31@ and @data20@ etc. can be used to initialize"
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print "memories in 16-bit buses, also split in byte columns.\n"
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print "memories in 16-bit buses, also split in byte columns.\n"
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print "Other template tags are replaced as follows:"
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print "Other template tags are replaced as follows:"
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print "@entity_name@ : Name of entity in target vhdl file"
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print "@entity_name@ : Name of entity in target vhdl file"
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print "@arch_name@ : Name of architecture in target vhdl file"
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print "@arch_name@ : Name of architecture in target vhdl file"
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print "@sim_len@ : Length of simulation in clock cycles"
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print "@sim_len@ : Length of simulation in clock cycles"
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print "@code_table_size@ : Size of code RAM block, in words"
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print "@code_table_size@ : Size of code RAM block, in words"
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print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@code_addr_size@ : ceil(Log2(@code_table_size@))"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_table_size@ : Size of data RAM block, in words"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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print "@data_addr_size@ : ceil(Log2(@data_table_size@))"
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def build_vhdl_flash_table(flash, table_size, indent_size):
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def build_vhdl_flash_table(flash, table_size, indent_size):
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# Build vhdl table for flash data
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# Build vhdl table for flash data
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# fill up empty table space with zeros
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# fill up empty table space with zeros
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if len(flash) < table_size*4:
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if len(flash) < table_size*4:
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flash = flash + '\0'*4*(table_size-len(flash)/4)
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flash = flash + '\0'*4*(table_size-len(flash)/4)
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num_words = len(flash)/4
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num_words = len(flash)/4
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remaining = num_words;
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remaining = num_words;
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col = 0
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col = 0
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vhdl_flash_string = "\n" + " "*indent_size
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vhdl_flash_string = "\n" + " "*indent_size
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for w in range(num_words):
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for w in range(num_words):
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b0 = ord(flash[w*4+0]);
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b0 = ord(flash[w*4+0]);
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b1 = ord(flash[w*4+1]);
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b1 = ord(flash[w*4+1]);
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b2 = ord(flash[w*4+2]);
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b2 = ord(flash[w*4+2]);
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b3 = ord(flash[w*4+3]);
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b3 = ord(flash[w*4+3]);
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if remaining > 1:
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if remaining > 1:
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item = "X\"%02X%02X%02X%02X\"," % (b0, b1, b2, b3)
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item = "X\"%02X%02X%02X%02X\"," % (b0, b1, b2, b3)
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else:
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else:
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item = "X\"%02X%02X%02X%02X\"" % (b0, b1, b2, b3)
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item = "X\"%02X%02X%02X%02X\"" % (b0, b1, b2, b3)
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remaining = remaining - 1
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remaining = remaining - 1
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col = col + 1
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col = col + 1
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if col == 4:
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if col == 4:
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col = 0
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col = 0
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item = item + "\n" + " "*indent_size
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item = item + "\n" + " "*indent_size
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vhdl_flash_string = vhdl_flash_string + item
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vhdl_flash_string = vhdl_flash_string + item
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return vhdl_flash_string
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return vhdl_flash_string
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def build_vhdl_tables(code,table_size, indent_size):
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def build_vhdl_tables(code,table_size, indent_size):
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# Build the four byte column tables. [0] is LSB, [3] is MSB
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# Build the four byte column tables. [0] is LSB, [3] is MSB
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# Useful only for BRAM and SRAM tables
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# Useful only for BRAM and SRAM tables
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tables = [[0 for i in range(table_size)] for i in range(4)]
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tables = [[0 for i in range(table_size)] for i in range(4)]
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# Separate binary data into byte columns
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# Separate binary data into byte columns
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# (here's where data endianess matters, we're assuming big endian)
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# (here's where data endianess matters, we're assuming big endian)
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byte = 0 # byte 0 is LSB, 3 is MSB
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byte = 0 # byte 0 is LSB, 3 is MSB
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index = 0 # index into column table
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index = 0 # index into column table
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for c in code:
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for c in code:
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#print str(ord(c)) + " " + str(byte) + " " + str(index)
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#print str(ord(c)) + " " + str(byte) + " " + str(index)
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tables[3-byte][index] = ord(c)
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tables[3-byte][index] = ord(c)
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#for k in tables:
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#for k in tables:
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# print k[0:4]
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# print k[0:4]
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byte = byte + 1
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byte = byte + 1
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if byte == 4:
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if byte == 4:
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byte = 0
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byte = 0
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index = index + 1
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index = index + 1
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# Write the data for each of the four column tables as a VHDL byte
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# Write the data for each of the four column tables as a VHDL byte
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# constant table.
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# constant table.
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vhdl_data_strings = [" "*indent_size]*7
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vhdl_data_strings = [" "*indent_size]*7
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for j in range(4):
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for j in range(4):
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col = 0
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col = 0
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word = len(tables[j])
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word = len(tables[j])
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for c in tables[j]:
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for c in tables[j]:
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word = word - 1
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word = word - 1
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if word > 0:
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if word > 0:
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item = "X\"%02X\"," % c
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item = "X\"%02X\"," % c
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else:
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else:
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item = "X\"%02X\"" % c
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item = "X\"%02X\"" % c
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col = col + 1
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col = col + 1
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if col == 8:
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if col == 8:
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col = 0
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col = 0
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item = item + "\n" + " "*indent_size
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item = item + "\n" + " "*indent_size
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vhdl_data_strings[j] = vhdl_data_strings[j] + item
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vhdl_data_strings[j] = vhdl_data_strings[j] + item
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vhdl_data_strings[j] = "\n" + vhdl_data_strings[j]
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vhdl_data_strings[j] = "\n" + vhdl_data_strings[j]
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# ok, now build init strings for 16-bit wide memories, split in 2 byte
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# ok, now build init strings for 16-bit wide memories, split in 2 byte
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# columns: an odd column with bytes 3:1 and an even column with bytes 2:0
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# columns: an odd column with bytes 3:1 and an even column with bytes 2:0
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byte_order = [3,1,2,0]
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byte_order = [3,1,2,0]
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for j in range(2):
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for j in range(2):
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col = 0
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col = 0
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word_count = len(tables[j*2])
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word_count = len(tables[j*2])
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for i in range(word_count):
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for i in range(word_count):
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w_high = tables[byte_order[j*2+0]][i]
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w_high = tables[byte_order[j*2+0]][i]
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w_low = tables[byte_order[j*2+1]][i]
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w_low = tables[byte_order[j*2+1]][i]
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word_count = word_count - 1
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word_count = word_count - 1
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if word_count > 0:
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if word_count > 0:
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item_h = "X\"%02X\"," % w_high
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item_h = "X\"%02X\"," % w_high
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item_l = "X\"%02X\"," % w_low
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item_l = "X\"%02X\"," % w_low
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else:
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else:
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item_h = "X\"%02X\"," % w_high
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item_h = "X\"%02X\"," % w_high
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item_l = "X\"%02X\"" % w_low
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item_l = "X\"%02X\"" % w_low
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item = item_h + item_l
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item = item_h + item_l
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col = col + 1
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col = col + 1
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if col == 4:
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if col == 4:
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col = 0
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col = 0
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item = item + "\n" + " "*indent_size
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item = item + "\n" + " "*indent_size
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vhdl_data_strings[4+j] = vhdl_data_strings[4+j] + item
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vhdl_data_strings[4+j] = vhdl_data_strings[4+j] + item
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vhdl_data_strings[4+j] = "\n" + vhdl_data_strings[4+j]
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vhdl_data_strings[4+j] = "\n" + vhdl_data_strings[4+j]
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# finally, build init strings for 32-bit wide memories not split into
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# finally, build init strings for 32-bit wide memories not split into
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# byte columns; useful for read-only 32-bit wide BRAMs
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# byte columns; useful for read-only 32-bit wide BRAMs
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byte_order = [3,2,1,0]
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byte_order = [3,2,1,0]
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col = 0
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col = 0
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word_count = len(tables[0])
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word_count = len(tables[0])
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for i in range(word_count):
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for i in range(word_count):
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w3 = tables[byte_order[0]][i]
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w3 = tables[byte_order[0]][i]
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w2 = tables[byte_order[1]][i]
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w2 = tables[byte_order[1]][i]
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w1 = tables[byte_order[2]][i]
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w1 = tables[byte_order[2]][i]
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w0 = tables[byte_order[3]][i]
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w0 = tables[byte_order[3]][i]
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word_count = word_count - 1
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word_count = word_count - 1
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if word_count > 0:
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if word_count > 0:
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item = "X\"%02X%02X%02X%02X\"," % (w3, w2, w1, w0)
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item = "X\"%02X%02X%02X%02X\"," % (w3, w2, w1, w0)
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else:
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else:
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item = "X\"%02X%02X%02X%02X\"" % (w3, w2, w1, w0)
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item = "X\"%02X%02X%02X%02X\"" % (w3, w2, w1, w0)
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col = col + 1
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col = col + 1
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if col == 4:
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if col == 4:
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col = 0
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col = 0
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item = item + "\n" + " "*indent_size
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item = item + "\n" + " "*indent_size
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vhdl_data_strings[6] = vhdl_data_strings[6] + item
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vhdl_data_strings[6] = vhdl_data_strings[6] + item
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vhdl_data_strings[6] = "\n" + vhdl_data_strings[6]
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vhdl_data_strings[6] = "\n" + vhdl_data_strings[6]
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return vhdl_data_strings
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return vhdl_data_strings
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def main(argv):
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def main(argv):
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code_filename = "" # file with bram contents ('code')
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code_filename = "" # file with bram contents ('code')
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data_filename = "" # file with xram contents ('data')
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data_filename = "" # file with xram contents ('data')
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flash_filename = "" # file with flash contents ('flash')
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flash_filename = "" # file with flash contents ('flash')
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vhdl_filename = "" # name of vhdl template file
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vhdl_filename = "" # name of vhdl template file
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entity_name = "mips_tb" # name of vhdl entity to be generated
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entity_name = "mips_tb" # name of vhdl entity to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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arch_name = "testbench" # name of vhdl architecture to be generated
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target_filename = "tb.vhdl" # name of target vhdl file
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target_filename = "tb.vhdl" # name of target vhdl file
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indent = 4 # indentation for table data, in spaces
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indent = 4 # indentation for table data, in spaces
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code_table_size = -1 # size of VHDL table
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code_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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data_table_size = -1 # size of VHDL table
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flash_table_size = 32; # default size of flash table in 32-bit words
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flash_table_size = 32; # default size of flash table in 32-bit words
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log_trigger_addr = "X\"FFFFFFFF\"" # default log trigger address
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log_trigger_addr = "X\"FFFFFFFF\"" # default log trigger address
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flash = ['\0']*4*flash_table_size # default simulated flash
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flash = ['\0']*4*flash_table_size # default simulated flash
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bin_words = 0 # size of binary file in 32-bit words
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bin_words = 0 # size of binary file in 32-bit words
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simulation_length = 22000 # length of logic simulation in clock cycles
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simulation_length = 22000 # length of logic simulation in clock cycles
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#
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#
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try:
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try:
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
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opts, args = getopt.getopt(argv, "hc:d:v:a:e:o:i:s:f:t:",
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["help", "code=", "data=", "vhdl=", "architecture=",
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["help", "code=", "data=", "vhdl=", "architecture=",
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"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
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"entity=", "output=", "indent=", "sim_len=", "flash=", "log_trigger=",
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"code_size=", "data_size=", "flash_size="])
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"code_size=", "data_size=", "flash_size="])
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except getopt.GetoptError, err:
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except getopt.GetoptError, err:
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print ""
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print ""
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print err
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print err
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usage()
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usage()
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sys.exit(2)
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sys.exit(2)
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# Parse coommand line parameters
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# Parse coommand line parameters
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for opt, arg in opts:
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for opt, arg in opts:
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if opt in ("-h", "--help"):
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if opt in ("-h", "--help"):
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usage()
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usage()
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help()
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help()
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exit(1)
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exit(1)
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if opt in ("-v", "--vhdl"):
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if opt in ("-v", "--vhdl"):
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vhdl_filename = arg
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vhdl_filename = arg
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elif opt in ("-o", "--output"):
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elif opt in ("-o", "--output"):
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target_filename = arg
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target_filename = arg
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elif opt in ("-c", "--code"):
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elif opt in ("-c", "--code"):
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code_filename = arg
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code_filename = arg
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elif opt in ("-d", "--data"):
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elif opt in ("-d", "--data"):
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data_filename = arg
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data_filename = arg
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elif opt in ("-f", "--flash"):
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elif opt in ("-f", "--flash"):
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flash_filename = arg
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flash_filename = arg
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elif opt in ("-a", "--architecture"):
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elif opt in ("-a", "--architecture"):
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arch_name = arg
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arch_name = arg
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elif opt in ("-e", "--entity"):
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elif opt in ("-e", "--entity"):
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entity_name = arg
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entity_name = arg
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elif opt in ("-i", "--indent"):
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elif opt in ("-i", "--indent"):
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indent = int(arg)
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indent = int(arg)
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elif opt in ("-t", "--log_trigger"):
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elif opt in ("-t", "--log_trigger"):
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log_trigger_addr = "X\"%08X\"" % (int(arg,16))
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log_trigger_addr = "X\"%08X\"" % (int(arg,16))
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elif opt in ("-s", "--sim_len"):
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elif opt in ("-s", "--sim_len"):
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simulation_length = int(arg)
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simulation_length = int(arg)
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elif opt == "--code_size":
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elif opt == "--code_size":
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code_table_size = int(arg)
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code_table_size = int(arg)
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elif opt == "--data_size":
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elif opt == "--data_size":
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data_table_size = int(arg)
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data_table_size = int(arg)
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elif opt == "--flash_size":
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elif opt == "--flash_size":
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flash_table_size = int(arg)
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flash_table_size = int(arg)
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# See if all mandatory options are there
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# See if all mandatory options are there
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if code_filename=="" or vhdl_filename=="" or \
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if code_filename=="" or vhdl_filename=="" or \
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code_table_size < 0 or data_table_size<0:
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code_table_size < 0 or data_table_size<0:
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print "Some mandatory parameter is missing\n"
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print "Some mandatory parameter is missing\n"
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usage()
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usage()
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sys.exit(2)
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sys.exit(2)
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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# Read BRAM initialization file, if any
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# Read BRAM initialization file, if any
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try:
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try:
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fin = open(code_filename, "rb")
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fin = open(code_filename, "rb")
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code = fin.read()
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code = fin.read()
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fin.close()
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fin.close()
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except IOError:
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except IOError:
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print "Binary File %s not found" % code_filename
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print "Binary File %s not found" % code_filename
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# Make sure the code and data will fit in the tables
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# Make sure the code and data will fit in the tables
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bin_words = len(code) / 4
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bin_words = len(code) / 4
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if bin_words > code_table_size:
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if bin_words > code_table_size:
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print "Code does not fit table: " + str(bin_words) + " words,",
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print "Code does not fit table: " + str(bin_words) + " words,",
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print str(code_table_size) + " table entries"
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print str(code_table_size) + " table entries"
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sys.exit(1)
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sys.exit(1)
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# Build the VHDL strings for each slice of the BRAM tables
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# Build the VHDL strings for each slice of the BRAM tables
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vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
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vhdl_code_strings = build_vhdl_tables(code, code_table_size, indent)
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#---------------------------------------------------------------------------
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#---------------------------------------------------------------------------
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# Read XRAM initialization file, if any.
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# Read XRAM initialization file, if any.
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if data_filename != "":
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if data_filename != "":
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if data_filename == "empty":
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if data_filename == "empty":
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data = []
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data = []
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else:
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else:
|
try:
|
try:
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fin = open(data_filename, "rb")
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fin = open(data_filename, "rb")
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data = fin.read()
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data = fin.read()
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fin.close()
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fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % data_filename
|
print "Binary File %s not found" % data_filename
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|
|
# FIXME We're not checking for BSS size here, only .data (?)
|
# FIXME We're not checking for BSS size here, only .data (?)
|
bin_words = len(data) / 4
|
bin_words = len(data) / 4
|
if bin_words > data_table_size:
|
if bin_words > data_table_size:
|
print "Data does not fit table: " + str(bin_words) + " words,",
|
print "Data does not fit table: " + str(bin_words) + " words,",
|
print str(data_table_size) + " table entries"
|
print str(data_table_size) + " table entries"
|
sys.exit(1)
|
sys.exit(1)
|
|
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
vhdl_data_strings = build_vhdl_tables(data, data_table_size, indent)
|
else:
|
else:
|
# In case we didn't get a data binary, we will initialize any XRAM in
|
# In case we didn't get a data binary, we will initialize any XRAM in
|
# the template with zeros
|
# the template with zeros
|
vhdl_data_strings = (["(others => X\"00\")"]*4) + \
|
vhdl_data_strings = (["(others => X\"00\")"]*4) + \
|
(["(others => X\"00\")"]*2) + \
|
(["(others => X\"00\")"]*2) + \
|
(["(others => X\"00000000\")"])
|
(["(others => X\"00000000\")"])
|
|
|
|
|
#---------------------------------------------------------------------------
|
#---------------------------------------------------------------------------
|
# Read FLASH initialization file, if any
|
# Read FLASH initialization file, if any
|
|
|
if flash_filename != "":
|
if flash_filename != "":
|
if flash_filename == "empty":
|
if flash_filename == "empty":
|
flash = [0]*flash_table_size
|
flash = [0]*flash_table_size
|
else:
|
else:
|
try:
|
try:
|
fin = open(flash_filename, "rb")
|
fin = open(flash_filename, "rb")
|
flash = fin.read()
|
flash = fin.read()
|
fin.close()
|
fin.close()
|
except IOError:
|
except IOError:
|
print "Binary File %s not found" % flash_filename
|
print "Binary File %s not found" % flash_filename
|
|
|
# make sure file will fit simulated FLASH size
|
# make sure file will fit simulated FLASH size
|
bin_words = len(flash) / 4
|
bin_words = len(flash) / 4
|
if bin_words > flash_table_size:
|
if bin_words > flash_table_size:
|
print "Flash data does not fit table: " + str(bin_words) + " words,",
|
print "Flash data does not fit table: " + str(bin_words) + " words,",
|
print str(flash_table_size) + " table entries"
|
print str(flash_table_size) + " table entries"
|
sys.exit(1)
|
sys.exit(1)
|
|
|
|
|
# Build the VHDL strings for the simulated FLASH
|
# Build the VHDL strings for the simulated FLASH
|
vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
|
vhdl_flash_string = build_vhdl_flash_table(flash, flash_table_size, indent)
|
|
|
|
|
#===========================================================================
|
#===========================================================================
|
# OK, we just read all binary files and built all VHDL memory initialization
|
# OK, we just read all binary files and built all VHDL memory initialization
|
# strings. Now start scanning the VHDL template, inserting data where needed
|
# strings. Now start scanning the VHDL template, inserting data where needed
|
|
|
# Read template file...
|
# Read template file...
|
fin = open(vhdl_filename, "r")
|
fin = open(vhdl_filename, "r")
|
vhdl_lines = fin.readlines()
|
vhdl_lines = fin.readlines()
|
fin.close()
|
fin.close()
|
|
|
# ...and build the keyword and replacement tables
|
# ...and build the keyword and replacement tables
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
keywords = ["@code0@","@code1@","@code2@","@code3@",
|
"@code31@", "@code20@",
|
"@code31@", "@code20@",
|
"@code-32bit@",
|
"@code-32bit@",
|
"@data0@","@data1@","@data2@","@data3@",
|
"@data0@","@data1@","@data2@","@data3@",
|
"@data31@", "@data20@",
|
"@data31@", "@data20@",
|
"@data-32bit@",
|
"@data-32bit@",
|
"@flash@",
|
"@flash@",
|
"@entity_name@","@arch_name@",
|
"@entity_name@","@arch_name@",
|
"@sim_len@",
|
"@sim_len@",
|
"@xram_size@",
|
"@xram_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@code_table_size@","@code_addr_size@",
|
"@data_table_size@","@data_addr_size@",
|
"@data_table_size@","@data_addr_size@",
|
"@prom_size@",
|
"@prom_size@",
|
"@log_trigger_addr@"];
|
"@log_trigger_addr@"];
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
replacement = vhdl_code_strings + vhdl_data_strings + \
|
[vhdl_flash_string,
|
[vhdl_flash_string,
|
entity_name, arch_name,
|
entity_name, arch_name,
|
str(simulation_length),
|
str(simulation_length),
|
str(data_table_size),
|
str(data_table_size),
|
str(code_table_size),
|
str(code_table_size),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(int(math.floor(math.log(code_table_size,2)))),
|
str(data_table_size),
|
str(data_table_size),
|
str(int(math.floor(math.log(data_table_size,2)))),
|
str(int(math.floor(math.log(data_table_size,2)))),
|
str(flash_table_size),
|
str(flash_table_size),
|
log_trigger_addr]
|
log_trigger_addr]
|
|
|
# Now traverse the template lines replacing any keywords with the proper
|
# Now traverse the template lines replacing any keywords with the proper
|
# vhdl stuff we just built above.
|
# vhdl stuff we just built above.
|
output = ""
|
output = ""
|
for vhdl_line in vhdl_lines:
|
for vhdl_line in vhdl_lines:
|
temp = vhdl_line
|
temp = vhdl_line
|
for i in range(len(keywords)):
|
for i in range(len(keywords)):
|
if temp.rfind(keywords[i]) >= 0:
|
if temp.rfind(keywords[i]) >= 0:
|
temp = temp.replace(keywords[i], replacement[i])
|
temp = temp.replace(keywords[i], replacement[i])
|
# uncomment this break to check for ONE keyword per line only
|
# uncomment this break to check for ONE keyword per line only
|
#break
|
#break
|
output = output + temp
|
output = output + temp
|
|
|
try:
|
try:
|
fout = open(target_filename, "w")
|
fout = open(target_filename, "w")
|
fout.write(output)
|
fout.write(output)
|
fout.close()
|
fout.close()
|
print "Wrote VHDL file '%s'" % target_filename
|
print "Wrote VHDL file '%s'" % target_filename
|
except IOError:
|
except IOError:
|
print "Could not write to file %s" % target_filename
|
print "Could not write to file %s" % target_filename
|
|
|
|
|
sys.exit(0)
|
sys.exit(0)
|
|
|
|
|
|
|
if __name__ == "__main__":
|
if __name__ == "__main__":
|
main(sys.argv[1:])
|
main(sys.argv[1:])
|
|
|
sys.exit(0)
|
sys.exit(0)
|
|
|
|
|
