--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This file was generated automatically from '/src/mips_mpu2_template.vhdl'.
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-- This file was generated automatically from '/src/mips_mpu2_template.vhdl'.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Synthesizable MPU -- CPU + cache + bootstrap BRAM + UART
|
-- Synthesizable MPU -- CPU + cache + bootstrap BRAM + UART
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--
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--
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-- This module uses the 'stub' version of the cache: a cache which actually is
|
-- This module uses the 'stub' version of the cache: a cache which actually is
|
-- only an interface between the cpu and external static memory. This is useful
|
-- only an interface between the cpu and external static memory. This is useful
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-- to test external memory interface and cache-cpu interface without the cache
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-- to test external memory interface and cache-cpu interface without the cache
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-- functionality getting in the way.
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-- functionality getting in the way.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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|
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entity mips_mpu is
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entity mips_mpu is
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generic (
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generic (
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|
CLOCK_FREQ : integer := 50000000;
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SRAM_ADDR_SIZE : integer := 17
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SRAM_ADDR_SIZE : integer := 17
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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interrupt : in std_logic;
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interrupt : in std_logic;
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_data : out std_logic_vector(31 downto 0);
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io_wr_data : out std_logic_vector(31 downto 0);
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io_rd_vma : out std_logic;
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io_rd_vma : out std_logic;
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io_byte_we : out std_logic_vector(3 downto 0);
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io_byte_we : out std_logic_vector(3 downto 0);
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
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sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
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sram_data_wr : out std_logic_vector(15 downto 0);
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sram_data_wr : out std_logic_vector(15 downto 0);
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sram_data_rd : in std_logic_vector(15 downto 0);
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sram_data_rd : in std_logic_vector(15 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_oe_n : out std_logic;
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sram_oe_n : out std_logic;
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-- UART
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-- UART
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uart_rxd : in std_logic;
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uart_rxd : in std_logic;
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uart_txd : out std_logic
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uart_txd : out std_logic
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);
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);
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end; --entity mips_mpu
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end; --entity mips_mpu
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architecture rtl of mips_mpu is
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architecture rtl of mips_mpu is
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-- interface cpu-cache
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-- interface cpu-cache
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signal cpu_data_addr : t_word;
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signal cpu_data_addr : t_word;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd : t_word;
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signal cpu_data_rd : t_word;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr : t_word;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_ic_invalidate : std_logic;
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signal cpu_cache_enable : std_logic;
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signal cpu_cache_enable : std_logic;
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-- interface to i/o
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-- interface to i/o
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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|
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-- interface to UARTs
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-- interface to UARTs
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signal uart_rd_word : t_word;
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signal uart_rd_word : t_word;
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signal uart_tx_rdy : std_logic := '1';
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_write : std_logic;
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signal uart_write : std_logic;
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signal uart_read : std_logic;
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signal uart_read : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_data_rx : std_logic_vector(7 downto 0);
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signal uart_data_rx : std_logic_vector(7 downto 0);
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|
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-- Block ram
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-- Block ram
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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|
|
--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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type t_bram is array(0 to (BRAM_SIZE)-1) of t_word;
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type t_bram is array(0 to (BRAM_SIZE)-1) of t_word;
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|
|
-- bram0 is LSB, bram3 is MSB
|
-- bram0 is LSB, bram3 is MSB
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--signal bram3 : t_bram := (@ code3@);
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--signal bram3 : t_bram := (@ code3@);
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--signal bram2 : t_bram := (@ code2@);
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--signal bram2 : t_bram := (@ code2@);
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--signal bram1 : t_bram := (@ code1@);
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--signal bram1 : t_bram := (@ code1@);
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--signal bram0 : t_bram := (@ code0@);
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--signal bram0 : t_bram := (@ code0@);
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|
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signal bram : t_bram := (@code-32bit@);
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signal bram : t_bram := (@code-32bit@);
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|
|
subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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|
|
signal bram_rd_addr : t_bram_address;
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signal bram_rd_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_rd_data : t_word;
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signal bram_rd_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_byte_we : std_logic_vector(3 downto 0);
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signal bram_byte_we : std_logic_vector(3 downto 0);
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|
|
|
|
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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begin
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begin
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|
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cpu: entity work.mips_cpu
|
cpu: entity work.mips_cpu
|
port map (
|
port map (
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interrupt => '0',
|
interrupt => '0',
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|
|
data_addr => cpu_data_addr,
|
data_addr => cpu_data_addr,
|
data_rd_vma => cpu_data_rd_vma,
|
data_rd_vma => cpu_data_rd_vma,
|
data_rd => cpu_data_rd,
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data_rd => cpu_data_rd,
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|
|
code_rd_addr=> cpu_code_rd_addr,
|
code_rd_addr=> cpu_code_rd_addr,
|
code_rd => cpu_code_rd,
|
code_rd => cpu_code_rd,
|
code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
|
|
|
data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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|
|
mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable=> cpu_cache_enable,
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cache_enable=> cpu_cache_enable,
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ic_invalidate=>cpu_ic_invalidate,
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ic_invalidate=>cpu_ic_invalidate,
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|
|
clk => clk,
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clk => clk,
|
reset => reset
|
reset => reset
|
);
|
);
|
|
|
cache: entity work.mips_cache_stub
|
cache: entity work.mips_cache_stub
|
generic map (
|
generic map (
|
BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
|
BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
|
SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
|
SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
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|
|
-- Interface to CPU core
|
-- Interface to CPU core
|
data_addr => cpu_data_addr,
|
data_addr => cpu_data_addr,
|
data_rd => cpu_data_rd,
|
data_rd => cpu_data_rd,
|
data_rd_vma => cpu_data_rd_vma,
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data_rd_vma => cpu_data_rd_vma,
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|
|
code_rd_addr => cpu_code_rd_addr,
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code_rd_addr => cpu_code_rd_addr,
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code_rd => cpu_code_rd,
|
code_rd => cpu_code_rd,
|
code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
|
|
|
byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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|
|
mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => cpu_cache_enable,
|
cache_enable => cpu_cache_enable,
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ic_invalidate => cpu_ic_invalidate,
|
ic_invalidate => cpu_ic_invalidate,
|
|
|
-- interface to FPGA i/o devices
|
-- interface to FPGA i/o devices
|
io_rd_data => mpu_io_rd_data,
|
io_rd_data => mpu_io_rd_data,
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io_wr_data => mpu_io_wr_data,
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io_wr_data => mpu_io_wr_data,
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io_rd_addr => mpu_io_rd_addr,
|
io_rd_addr => mpu_io_rd_addr,
|
io_wr_addr => mpu_io_wr_addr,
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io_wr_addr => mpu_io_wr_addr,
|
io_rd_vma => mpu_io_rd_vma,
|
io_rd_vma => mpu_io_rd_vma,
|
io_byte_we => mpu_io_byte_we,
|
io_byte_we => mpu_io_byte_we,
|
|
|
-- interface to synchronous 32-bit-wide FPGA BRAM
|
-- interface to synchronous 32-bit-wide FPGA BRAM
|
bram_rd_data => bram_rd_data,
|
bram_rd_data => bram_rd_data,
|
bram_wr_data => bram_wr_data,
|
bram_wr_data => bram_wr_data,
|
bram_rd_addr => bram_rd_addr,
|
bram_rd_addr => bram_rd_addr,
|
bram_wr_addr => bram_wr_addr,
|
bram_wr_addr => bram_wr_addr,
|
bram_byte_we => bram_byte_we,
|
bram_byte_we => bram_byte_we,
|
|
|
-- interface to asynchronous 16-bit-wide external SRAM
|
-- interface to asynchronous 16-bit-wide external SRAM
|
sram_address => sram_address,
|
sram_address => sram_address,
|
sram_data_rd => sram_data_rd,
|
sram_data_rd => sram_data_rd,
|
sram_data_wr => sram_data_wr,
|
sram_data_wr => sram_data_wr,
|
sram_byte_we_n => sram_byte_we_n,
|
sram_byte_we_n => sram_byte_we_n,
|
sram_oe_n => sram_oe_n
|
sram_oe_n => sram_oe_n
|
);
|
);
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- BRAM interface
|
-- BRAM interface
|
|
|
fpga_ram_block:
|
fpga_ram_block:
|
process(clk)
|
process(clk)
|
begin
|
begin
|
if clk'event and clk='1' then
|
if clk'event and clk='1' then
|
|
|
--bram_rd_data <=
|
--bram_rd_data <=
|
-- bram3(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram3(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram2(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram2(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram1(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram1(conv_integer(unsigned(bram_rd_addr))) &
|
-- bram0(conv_integer(unsigned(bram_rd_addr)));
|
-- bram0(conv_integer(unsigned(bram_rd_addr)));
|
bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
|
bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
|
|
|
end if;
|
end if;
|
end process fpga_ram_block;
|
end process fpga_ram_block;
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
serial_rx : entity work.rs232_rx
|
serial_rx : entity work.rs232_rx
|
|
generic map (
|
|
CLOCK_FREQ => CLOCK_FREQ
|
|
)
|
port map(
|
port map(
|
rxd => uart_rxd,
|
rxd => uart_rxd,
|
data_rx => uart_data_rx,
|
data_rx => uart_data_rx,
|
rx_rdy => uart_rx_rdy,
|
rx_rdy => uart_rx_rdy,
|
read_rx => uart_read_rx,
|
read_rx => uart_read_rx,
|
clk => clk,
|
clk => clk,
|
reset => reset
|
reset => reset
|
);
|
);
|
|
|
|
|
-- '1'-> Read some UART register (0x2---0---)
|
-- '1'-> Read some UART register (0x2---0---)
|
uart_read <= '1'
|
uart_read <= '1'
|
when mpu_io_rd_vma='1' and
|
when mpu_io_rd_vma='1' and
|
mpu_io_rd_addr(31 downto 28)=X"2" and
|
mpu_io_rd_addr(31 downto 28)=X"2" and
|
mpu_io_rd_addr(15 downto 12)=X"0"
|
mpu_io_rd_addr(15 downto 12)=X"0"
|
else '0';
|
else '0';
|
|
|
-- '1'-> Read UART Rx data (0x2---0-0-)
|
-- '1'-> Read UART Rx data (0x2---0-0-)
|
-- (This signal clears the RX 1-char buffer)
|
-- (This signal clears the RX 1-char buffer)
|
uart_read_rx <= '1'
|
uart_read_rx <= '1'
|
when uart_read='1' and
|
when uart_read='1' and
|
mpu_io_rd_addr( 7 downto 4)=X"0"
|
mpu_io_rd_addr( 7 downto 4)=X"0"
|
else '0';
|
else '0';
|
|
|
-- '1'-> Write UART Tx register (trigger UART Tx) (0x20000000)
|
-- '1'-> Write UART Tx register (trigger UART Tx) (0x20000000)
|
uart_write <= '1'
|
uart_write <= '1'
|
when mpu_io_byte_we/="0000" and
|
when mpu_io_byte_we/="0000" and
|
mpu_io_wr_addr(31 downto 28)=X"2" and
|
mpu_io_wr_addr(31 downto 28)=X"2" and
|
mpu_io_wr_addr(15 downto 12)=X"0"
|
mpu_io_wr_addr(15 downto 12)=X"0"
|
else '0';
|
else '0';
|
|
|
serial_tx : entity work.rs232_tx
|
serial_tx : entity work.rs232_tx
|
|
generic map (
|
|
CLOCK_FREQ => CLOCK_FREQ
|
|
)
|
port map(
|
port map(
|
clk => clk,
|
clk => clk,
|
reset => reset,
|
reset => reset,
|
rdy => uart_tx_rdy,
|
rdy => uart_tx_rdy,
|
load => uart_write,
|
load => uart_write,
|
data_i => mpu_io_wr_data(7 downto 0),
|
data_i => mpu_io_wr_data(7 downto 0),
|
txd => uart_txd
|
txd => uart_txd
|
);
|
);
|
|
|
-- Both UART rd addresses 000 and 020 read the same word (save a mux), but only
|
-- Both UART rd addresses 000 and 020 read the same word (save a mux), but only
|
-- address 000 clears the rx buffer.
|
-- address 000 clears the rx buffer.
|
uart_rd_word <= uart_data_rx & X"00000" & "00" & uart_tx_rdy & uart_rx_rdy;
|
uart_rd_word <= uart_data_rx & X"00000" & "00" & uart_tx_rdy & uart_rx_rdy;
|
|
|
-- IO Rd mux: either the UART data/status word od the IO coming from outside
|
-- IO Rd mux: either the UART data/status word od the IO coming from outside
|
mpu_io_rd_data <=
|
mpu_io_rd_data <=
|
uart_rd_word when mpu_io_rd_addr(15 downto 12)=X"0" else
|
uart_rd_word when mpu_io_rd_addr(15 downto 12)=X"0" else
|
io_rd_data;
|
io_rd_data;
|
|
|
-- io_rd_data
|
-- io_rd_data
|
io_rd_addr <= mpu_io_rd_addr;
|
io_rd_addr <= mpu_io_rd_addr;
|
io_wr_addr <= mpu_io_wr_addr;
|
io_wr_addr <= mpu_io_wr_addr;
|
io_wr_data <= mpu_io_wr_data;
|
io_wr_data <= mpu_io_wr_data;
|
io_rd_vma <= mpu_io_rd_vma;
|
io_rd_vma <= mpu_io_rd_vma;
|
io_byte_we <= mpu_io_byte_we;
|
io_byte_we <= mpu_io_byte_we;
|
|
|
|
|
end architecture rtl;
|
end architecture rtl;
|
|
|