--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- This file was generated automatically from '/src/mips_mpu2_template.vhdl'.
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-- This file was generated automatically from '/src/mips_mpu2_template.vhdl'.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Synthesizable MPU -- CPU + cache + bootstrap BRAM + UART
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-- Synthesizable MPU -- CPU + cache + bootstrap BRAM + UART
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--
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--
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-- This module uses the 'stub' version of the cache: a cache which actually is
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-- This module uses the 'stub' version of the cache: a cache which actually is
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-- only an interface between the cpu and external static memory. This is useful
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-- only an interface between the cpu and external static memory. This is useful
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-- to test external memory interface and cache-cpu interface without the cache
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-- to test external memory interface and cache-cpu interface without the cache
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-- functionality getting in the way.
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-- functionality getting in the way.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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entity mips_mpu is
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entity mips_mpu is
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generic (
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generic (
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SRAM_ADDR_SIZE : integer := 17
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SRAM_ADDR_SIZE : integer := 17
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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interrupt : in std_logic;
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interrupt : in std_logic;
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_data : in std_logic_vector(31 downto 0);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_rd_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_addr : out std_logic_vector(31 downto 2);
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io_wr_data : out std_logic_vector(31 downto 0);
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io_wr_data : out std_logic_vector(31 downto 0);
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io_rd_vma : out std_logic;
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io_rd_vma : out std_logic;
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io_byte_we : out std_logic_vector(3 downto 0);
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io_byte_we : out std_logic_vector(3 downto 0);
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
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sram_address : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
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sram_databus : inout std_logic_vector(15 downto 0);
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sram_databus : inout std_logic_vector(15 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_byte_we_n : out std_logic_vector(1 downto 0);
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sram_oe_n : out std_logic;
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sram_oe_n : out std_logic;
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-- UART
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-- UART
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uart_rxd : in std_logic;
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uart_rxd : in std_logic;
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uart_txd : out std_logic
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uart_txd : out std_logic
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);
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);
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end; --entity mips_mpu
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end; --entity mips_mpu
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architecture rtl of mips_mpu is
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architecture rtl of mips_mpu is
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signal reset_sync : std_logic_vector(2 downto 0);
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-- interface cpu-cache
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-- interface cpu-cache
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signal cpu_data_rd_addr : t_word;
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signal cpu_data_rd_addr : t_word;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd_vma : std_logic;
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signal cpu_data_rd : t_word;
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signal cpu_data_rd : t_word;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd_addr : t_pc;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd : t_word;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_code_rd_vma : std_logic;
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signal cpu_data_wr_addr : t_pc;
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signal cpu_data_wr_addr : t_pc;
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signal cpu_data_wr : t_word;
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signal cpu_data_wr : t_word;
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_byte_we : std_logic_vector(3 downto 0);
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signal cpu_mem_wait : std_logic;
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signal cpu_mem_wait : std_logic;
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-- interface to i/o
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-- interface to i/o
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_wr_data : std_logic_vector(31 downto 0);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_wr_addr : std_logic_vector(31 downto 2);
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_rd_vma : std_logic;
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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signal mpu_io_byte_we : std_logic_vector(3 downto 0);
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-- interface to UARTs
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-- interface to UARTs
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signal data_uart : t_word;
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signal data_uart : t_word;
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signal data_uart_status : t_word;
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signal data_uart_status : t_word;
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signal uart_tx_rdy : std_logic := '1';
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_write_tx : std_logic;
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signal uart_write_tx : std_logic;
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signal uart_read_rx : std_logic;
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signal uart_read_rx : std_logic;
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-- Block ram
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-- Block ram
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_SIZE : integer := @code_table_size@;
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE);
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--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0);
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type t_bram is array(0 to (BRAM_SIZE)-1) of t_word;
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type t_bram is array(0 to (BRAM_SIZE)-1) of t_word;
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-- bram0 is LSB, bram3 is MSB
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-- bram0 is LSB, bram3 is MSB
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--signal bram3 : t_bram := (@ code3@);
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--signal bram3 : t_bram := (@ code3@);
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--signal bram2 : t_bram := (@ code2@);
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--signal bram2 : t_bram := (@ code2@);
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--signal bram1 : t_bram := (@ code1@);
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--signal bram1 : t_bram := (@ code1@);
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--signal bram0 : t_bram := (@ code0@);
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--signal bram0 : t_bram := (@ code0@);
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signal bram : t_bram := (@code-32bit@);
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signal bram : t_bram := (@code-32bit@);
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0);
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signal bram_rd_addr : t_bram_address;
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signal bram_rd_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_wr_addr : t_bram_address;
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signal bram_rd_data : t_word;
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signal bram_rd_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_wr_data : t_word;
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signal bram_byte_we : std_logic_vector(3 downto 0);
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signal bram_byte_we : std_logic_vector(3 downto 0);
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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begin
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begin
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cpu: entity work.mips_cpu
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cpu: entity work.mips_cpu
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port map (
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port map (
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interrupt => '0',
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interrupt => '0',
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data_rd_addr=> cpu_data_rd_addr,
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data_rd_addr=> cpu_data_rd_addr,
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data_rd_vma => cpu_data_rd_vma,
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data_rd_vma => cpu_data_rd_vma,
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data_rd => cpu_data_rd,
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data_rd => cpu_data_rd,
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code_rd_addr=> cpu_code_rd_addr,
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code_rd_addr=> cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
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data_wr_addr=> cpu_data_wr_addr,
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data_wr_addr=> cpu_data_wr_addr,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
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);
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);
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cache: entity work.mips_cache_stub
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cache: entity work.mips_cache_stub
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generic map (
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generic map (
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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BRAM_ADDR_SIZE => BRAM_ADDR_SIZE,
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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)
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)
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port map (
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port map (
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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-- Interface to CPU core
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-- Interface to CPU core
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data_rd_addr => cpu_data_rd_addr,
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data_rd_addr => cpu_data_rd_addr,
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data_rd => cpu_data_rd,
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data_rd => cpu_data_rd,
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data_rd_vma => cpu_data_rd_vma,
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data_rd_vma => cpu_data_rd_vma,
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code_rd_addr => cpu_code_rd_addr,
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code_rd_addr => cpu_code_rd_addr,
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code_rd => cpu_code_rd,
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code_rd => cpu_code_rd,
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code_rd_vma => cpu_code_rd_vma,
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code_rd_vma => cpu_code_rd_vma,
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data_wr_addr => cpu_data_wr_addr,
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data_wr_addr => cpu_data_wr_addr,
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byte_we => cpu_byte_we,
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byte_we => cpu_byte_we,
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data_wr => cpu_data_wr,
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data_wr => cpu_data_wr,
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mem_wait => cpu_mem_wait,
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mem_wait => cpu_mem_wait,
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cache_enable => '1',
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cache_enable => '1',
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data => mpu_io_rd_data,
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io_rd_data => mpu_io_rd_data,
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io_wr_data => mpu_io_wr_data,
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io_wr_data => mpu_io_wr_data,
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io_rd_addr => mpu_io_rd_addr,
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io_rd_addr => mpu_io_rd_addr,
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io_wr_addr => mpu_io_wr_addr,
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io_wr_addr => mpu_io_wr_addr,
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io_rd_vma => mpu_io_rd_vma,
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io_rd_vma => mpu_io_rd_vma,
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io_byte_we => mpu_io_byte_we,
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io_byte_we => mpu_io_byte_we,
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-- interface to synchronous 32-bit-wide FPGA BRAM
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-- interface to synchronous 32-bit-wide FPGA BRAM
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bram_rd_data => bram_rd_data,
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bram_rd_data => bram_rd_data,
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bram_wr_data => bram_wr_data,
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bram_wr_data => bram_wr_data,
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bram_rd_addr => bram_rd_addr,
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bram_rd_addr => bram_rd_addr,
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bram_wr_addr => bram_wr_addr,
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bram_wr_addr => bram_wr_addr,
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bram_byte_we => bram_byte_we,
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bram_byte_we => bram_byte_we,
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-- interface to asynchronous 16-bit-wide external SRAM
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-- interface to asynchronous 16-bit-wide external SRAM
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sram_address => sram_address,
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sram_address => sram_address,
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sram_databus => sram_databus,
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sram_databus => sram_databus,
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sram_byte_we_n => sram_byte_we_n,
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sram_byte_we_n => sram_byte_we_n,
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sram_oe_n => sram_oe_n
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sram_oe_n => sram_oe_n
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);
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);
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- BRAM interface
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-- BRAM interface
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fpga_ram_block:
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fpga_ram_block:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--bram_rd_data <=
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--bram_rd_data <=
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-- bram3(conv_integer(unsigned(bram_rd_addr))) &
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-- bram3(conv_integer(unsigned(bram_rd_addr))) &
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-- bram2(conv_integer(unsigned(bram_rd_addr))) &
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-- bram2(conv_integer(unsigned(bram_rd_addr))) &
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-- bram1(conv_integer(unsigned(bram_rd_addr))) &
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-- bram1(conv_integer(unsigned(bram_rd_addr))) &
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-- bram0(conv_integer(unsigned(bram_rd_addr)));
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-- bram0(conv_integer(unsigned(bram_rd_addr)));
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bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
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bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr)));
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end if;
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end if;
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end process fpga_ram_block;
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end process fpga_ram_block;
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-- FIXME this should be in parent block
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reset_synchronization:
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process(clk)
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begin
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if clk'event and clk='1' then
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reset_sync(2) <= reset;
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reset_sync(1) <= reset_sync(2);
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reset_sync(0) <= reset_sync(1);
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end if;
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end process reset_synchronization;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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serial_rx : entity work.rs232_rx
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serial_rx : entity work.rs232_rx
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port map(
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port map(
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rxd => uart_rxd,
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rxd => uart_rxd,
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data_rx => OPEN, --rs232_data_rx,
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data_rx => OPEN, --rs232_data_rx,
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rx_rdy => uart_rx_rdy,
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rx_rdy => uart_rx_rdy,
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read_rx => '1', --read_rx,
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read_rx => '1', --read_rx,
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clk => clk,
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clk => clk,
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reset => reset_sync(0)
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reset => reset
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);
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);
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uart_write_tx <= '1'
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uart_write_tx <= '1'
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when mpu_io_byte_we/="0000" and mpu_io_wr_addr(31 downto 28)=X"2"
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when mpu_io_byte_we/="0000" and mpu_io_wr_addr(31 downto 28)=X"2"
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else '0';
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else '0';
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serial_tx : entity work.rs232_tx
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serial_tx : entity work.rs232_tx
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port map(
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port map(
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clk => clk,
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clk => clk,
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reset => reset_sync(0),
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reset => reset,
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rdy => uart_tx_rdy,
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rdy => uart_tx_rdy,
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load => uart_write_tx,
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load => uart_write_tx,
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data_i => mpu_io_wr_data(7 downto 0),
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data_i => mpu_io_wr_data(7 downto 0),
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txd => uart_txd
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txd => uart_txd
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);
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);
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-- UART read registers; only status, and hardwired, for the time being
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-- UART read registers; only status, and hardwired, for the time being
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data_uart <= data_uart_status; -- FIXME no data rx yet
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data_uart <= data_uart_status; -- FIXME no data rx yet
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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mpu_io_rd_data <= data_uart;
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mpu_io_rd_data <= data_uart;
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-- io_rd_data
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-- io_rd_data
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io_rd_addr <= mpu_io_rd_addr;
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io_rd_addr <= mpu_io_rd_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_addr <= mpu_io_wr_addr;
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io_wr_data <= mpu_io_wr_data;
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io_wr_data <= mpu_io_wr_data;
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io_rd_vma <= mpu_io_rd_vma;
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io_rd_vma <= mpu_io_rd_vma;
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io_byte_we <= mpu_io_byte_we;
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io_byte_we <= mpu_io_byte_we;
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end architecture rtl;
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end architecture rtl;
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