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https://opencores.org/ocsvn/ion/ion/trunk
[/] [ion/] [trunk/] [src/] [opcodes/] [readme.txt] - Diff between revs 34 and 66
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This is a basic opcode test bench which tries all supported opcodes. See the
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This is a basic opcode test bench which tries all supported opcodes. See the
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source comments. This code has been lifted whole from the Plasma project.
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source comments. This code has been lifted whole from the Plasma project.
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Build the program with:
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Build the program with:
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make opcodes
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make opcodes
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or
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or
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make opcodes_sim
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make opcodes_sim
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Read ../readme.txt for some warnings on the makefile configuration.
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Read ../readme.txt for some warnings on the makefile configuration.
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The makefile will build a binary that you can run in the software simulator:
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It will build a vhdl test bench at /vhdl/tb/mips_tb2.vhdl (overwriting) that you
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can try on your VHDL simulator with script sim_tb2.do. The provided script and
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the VHDL code have some dependence on Modelsim, see project readme file.
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slite opcodes.bin
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It will build a vhdl test bench at /vhdl/tb/mips_tb1.vhdl (overwriting) that you
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The makefile will too bouild some bionaries that you can run in the software
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can try on your VHDL simulator with script sim_tb1.do. The provided script and
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simulator:
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the VHDL code have some dependence on Modelsim, see project readme file.
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slite --bram=opcodes.bin --xram=opcodes.data
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This code can't be used on real hardware (i/o is far too simple).
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This code can't be used on real hardware (i/o is far too simple).
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WARNING: the gnu assembler expands DIV* instructions, inserting code that
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WARNING: the gnu assembler expands DIV* instructions, inserting code that
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handles division by zero. Bear that in mind when reading the listing file.
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handles division by zero. Bear that in mind when reading the listing file.
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