--##############################################################################
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--##############################################################################
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
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--##############################################################################
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--##############################################################################
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-- This module is little more than a wrapper around the CPU and its memories.
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-- This module is little more than a wrapper around the CPU and its memories.
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--##############################################################################
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--##############################################################################
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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-- FPGA i/o for Terasic DE-1 board
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-- FPGA i/o for Terasic DE-1 board
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-- (Many of the board's i/o devices will go unused in this demo)
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-- (Many of the board's i/o devices will go unused in this demo)
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entity c2sb_demo is
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entity c2sb_demo is
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port (
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port (
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-- ***** Clocks
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-- ***** Clocks
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clk_50MHz : in std_logic;
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clk_50MHz : in std_logic;
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-- ***** Flash 4MB
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-- ***** Flash 4MB
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flash_addr : out std_logic_vector(21 downto 0);
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flash_addr : out std_logic_vector(21 downto 0);
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flash_data : in std_logic_vector(7 downto 0);
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flash_data : in std_logic_vector(7 downto 0);
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flash_oe_n : out std_logic;
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flash_oe_n : out std_logic;
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flash_we_n : out std_logic;
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flash_we_n : out std_logic;
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flash_reset_n : out std_logic;
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flash_reset_n : out std_logic;
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|
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-- ***** SRAM 256K x 16
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-- ***** SRAM 256K x 16
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sram_addr : out std_logic_vector(17 downto 0);
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sram_addr : out std_logic_vector(17 downto 0);
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sram_data : inout std_logic_vector(15 downto 0);
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sram_data : inout std_logic_vector(15 downto 0);
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sram_oe_n : out std_logic;
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sram_oe_n : out std_logic;
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sram_ub_n : out std_logic;
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sram_ub_n : out std_logic;
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sram_lb_n : out std_logic;
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sram_lb_n : out std_logic;
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sram_ce_n : out std_logic;
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sram_ce_n : out std_logic;
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sram_we_n : out std_logic;
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sram_we_n : out std_logic;
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|
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-- ***** RS-232
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-- ***** RS-232
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rxd : in std_logic;
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rxd : in std_logic;
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txd : out std_logic;
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txd : out std_logic;
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|
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-- ***** Switches and buttons
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-- ***** Switches and buttons
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switches : in std_logic_vector(9 downto 0);
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switches : in std_logic_vector(9 downto 0);
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buttons : in std_logic_vector(3 downto 0);
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buttons : in std_logic_vector(3 downto 0);
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|
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-- ***** Quad 7-seg displays
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-- ***** Quad 7-seg displays
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hex0 : out std_logic_vector(0 to 6);
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hex0 : out std_logic_vector(0 to 6);
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hex1 : out std_logic_vector(0 to 6);
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hex1 : out std_logic_vector(0 to 6);
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hex2 : out std_logic_vector(0 to 6);
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hex2 : out std_logic_vector(0 to 6);
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hex3 : out std_logic_vector(0 to 6);
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hex3 : out std_logic_vector(0 to 6);
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|
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-- ***** Leds
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-- ***** Leds
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red_leds : out std_logic_vector(9 downto 0);
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red_leds : out std_logic_vector(9 downto 0);
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green_leds : out std_logic_vector(7 downto 0);
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green_leds : out std_logic_vector(7 downto 0);
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|
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-- ***** SD Card
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-- ***** SD Card
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sd_data : in std_logic;
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sd_data : in std_logic;
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sd_cs : out std_logic;
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sd_cs : out std_logic;
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sd_cmd : out std_logic;
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sd_cmd : out std_logic;
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sd_clk : out std_logic
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sd_clk : out std_logic
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);
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);
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end c2sb_demo;
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end c2sb_demo;
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architecture minimal of c2sb_demo is
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architecture minimal of c2sb_demo is
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|
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--##############################################################################
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--##############################################################################
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--
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--
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|
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constant SRAM_ADDR_SIZE : integer := 18;
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constant SRAM_ADDR_SIZE : integer := 18;
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|
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--##############################################################################
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--##############################################################################
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-- RS232 interface signals
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-- RS232 interface signals
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|
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signal rx_rdy : std_logic;
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signal rx_rdy : std_logic;
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signal tx_rdy : std_logic;
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signal tx_rdy : std_logic;
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signal rs232_data_rx : std_logic_vector(7 downto 0);
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signal rs232_data_rx : std_logic_vector(7 downto 0);
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signal rs232_status : std_logic_vector(7 downto 0);
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signal rs232_status : std_logic_vector(7 downto 0);
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signal data_io_out : std_logic_vector(7 downto 0);
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signal data_io_out : std_logic_vector(7 downto 0);
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signal io_port : std_logic_vector(7 downto 0);
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signal io_port : std_logic_vector(7 downto 0);
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signal read_rx : std_logic;
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signal read_rx : std_logic;
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signal write_tx : std_logic;
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signal write_tx : std_logic;
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|
|
|
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--##############################################################################
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--##############################################################################
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--
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--
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|
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-- CPU access to hex display (unused by Altair SW)
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-- CPU access to hex display
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signal reg_display : std_logic_vector(15 downto 0);
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signal reg_display : std_logic_vector(15 downto 0);
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|
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|
|
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--##############################################################################
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--##############################################################################
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-- DE-1 board interface signals
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-- DE-1 board interface signals
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|
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-- Synchronization FF chain for asynchronous reset input
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signal reset_sync : std_logic_vector(2 downto 0);
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|
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-- Quad 7-segment display (non multiplexed) & LEDS
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-- Quad 7-segment display (non multiplexed) & LEDS
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signal display_data : std_logic_vector(15 downto 0);
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signal display_data : std_logic_vector(15 downto 0);
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signal reg_gleds : std_logic_vector(7 downto 0);
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signal reg_gleds : std_logic_vector(7 downto 0);
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|
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-- i/o signals
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signal data_io_in : std_logic_vector(7 downto 0);
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signal data_mem_in : std_logic_vector(7 downto 0);
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signal data_rom_in : std_logic_vector(7 downto 0);
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signal rom_access : std_logic;
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signal rom_space : std_logic;
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signal breakpoint : std_logic;
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|
|
|
|
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-- Clock & reset signals
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-- Clock & reset signals
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signal clk_1hz : std_logic;
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signal clk_1hz : std_logic;
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signal clk_master : std_logic;
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signal clk_master : std_logic;
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signal counter_1hz : std_logic_vector(25 downto 0);
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signal counter_1hz : std_logic_vector(25 downto 0);
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signal reset : std_logic;
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signal reset : std_logic;
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signal clk : std_logic;
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signal clk : std_logic;
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|
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-- SD control signals
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-- SD control signals
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signal sd_in : std_logic;
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signal sd_in : std_logic;
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signal reg_sd_dout : std_logic;
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signal reg_sd_dout : std_logic;
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signal reg_sd_clk : std_logic;
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signal reg_sd_clk : std_logic;
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signal reg_sd_cs : std_logic;
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signal reg_sd_cs : std_logic;
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|
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-- MPU interface signals
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-- MPU interface signals
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal uart_tx_rdy : std_logic := '1';
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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|
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signal io_rd_data : std_logic_vector(31 downto 0);
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signal io_rd_data : std_logic_vector(31 downto 0);
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signal io_rd_addr : std_logic_vector(31 downto 2);
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signal io_rd_addr : std_logic_vector(31 downto 2);
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signal io_wr_addr : std_logic_vector(31 downto 2);
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signal io_wr_addr : std_logic_vector(31 downto 2);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_rd_vma : std_logic;
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signal io_rd_vma : std_logic;
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signal io_byte_we : std_logic_vector(3 downto 0);
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signal io_byte_we : std_logic_vector(3 downto 0);
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|
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signal mpu_sram_address : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal mpu_sram_address : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal mpu_sram_databus : std_logic_vector(15 downto 0);
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signal mpu_sram_databus : std_logic_vector(15 downto 0);
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signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
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signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
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signal mpu_sram_oe_n : std_logic;
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signal mpu_sram_oe_n : std_logic;
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|
|
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-- Converts hex nibble to 7-segment
|
|
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
|
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function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
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return std_logic_vector is
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|
begin
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case nibble is
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when X"0" => return "0000001";
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when X"1" => return "1001111";
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when X"2" => return "0010010";
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when X"3" => return "0000110";
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when X"4" => return "1001100";
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when X"5" => return "0100100";
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when X"6" => return "0100000";
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when X"7" => return "0001111";
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when X"8" => return "0000000";
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when X"9" => return "0000100";
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when X"a" => return "0001000";
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when X"b" => return "1100000";
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when X"c" => return "0110001";
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when X"d" => return "1000010";
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when X"e" => return "0110000";
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when X"f" => return "0111000";
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when others => return "0111111"; -- can't happen
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end case;
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end function nibble_to_7seg;
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|
|
|
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begin
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begin
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|
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mpu: entity work.mips_mpu
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mpu: entity work.mips_mpu
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generic map (
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generic map (
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
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)
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)
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port map (
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port map (
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interrupt => '0',
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interrupt => '0',
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|
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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io_rd_data => io_rd_data,
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io_rd_data => io_rd_data,
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io_rd_addr => io_rd_addr,
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io_rd_addr => io_rd_addr,
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io_wr_addr => io_wr_addr,
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io_wr_addr => io_wr_addr,
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io_wr_data => io_wr_data,
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io_wr_data => io_wr_data,
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io_rd_vma => io_rd_vma,
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io_rd_vma => io_rd_vma,
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io_byte_we => io_byte_we,
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io_byte_we => io_byte_we,
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|
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address => mpu_sram_address,
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sram_address => mpu_sram_address,
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sram_databus => sram_data,
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sram_databus => sram_data,
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sram_byte_we_n => mpu_sram_byte_we_n,
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sram_byte_we_n => mpu_sram_byte_we_n,
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sram_oe_n => mpu_sram_oe_n,
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sram_oe_n => mpu_sram_oe_n,
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|
|
|
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uart_rxd => rxd,
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uart_rxd => rxd,
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uart_txd => txd,
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uart_txd => txd,
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|
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clk => clk,
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clk => clk,
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reset => reset
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reset => reset
|
);
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);
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|
|
|
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reg_display <= io_wr_data(15 downto 0);
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reg_display <= io_wr_data(15 downto 0);
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reg_gleds <= io_rd_vma & "000" & io_byte_we;
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reg_gleds <= io_rd_vma & "000" & io_byte_we;
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|
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-- red leds (light with '1') -- some CPU control signals
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-- red leds (light with '1') -- some CPU control signals
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red_leds(0) <= '0';
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red_leds(0) <= '0';
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red_leds(1) <= '0';
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red_leds(1) <= '0';
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red_leds(2) <= '0';
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red_leds(2) <= '0';
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red_leds(3) <= '0';
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red_leds(3) <= '0';
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red_leds(4) <= '0';
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red_leds(4) <= '0';
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red_leds(5) <= '0';
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red_leds(5) <= '0';
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red_leds(6) <= '0';
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red_leds(6) <= '0';
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red_leds(7) <= '0';
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red_leds(7) <= '0';
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red_leds(8) <= '0';
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red_leds(8) <= '0';
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red_leds(9) <= clk_1hz;
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red_leds(9) <= clk_1hz;
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|
|
|
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--##############################################################################
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--##############################################################################
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-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
|
-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
|
--##############################################################################
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--##############################################################################
|
|
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--##############################################################################
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--##############################################################################
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-- FLASH (flash is unused in this demo)
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-- FLASH (flash is unused in this demo)
|
--##############################################################################
|
--##############################################################################
|
|
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flash_addr <= (others => '0');
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flash_addr <= (others => '0');
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flash_we_n <= '1'; -- all enable signals inactive
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flash_we_n <= '1'; -- all enable signals inactive
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flash_oe_n <= '1';
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flash_oe_n <= '1';
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flash_reset_n <= '1';
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flash_reset_n <= '1';
|
|
|
|
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--##############################################################################
|
--##############################################################################
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-- SRAM (used as 64K x 8)
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-- SRAM (used as 64K x 8)
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--
|
--
|
-- NOTE: All writes go to SRAM independent of rom paging status
|
-- NOTE: All writes go to SRAM independent of rom paging status
|
--##############################################################################
|
--##############################################################################
|
|
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sram_addr <= mpu_sram_address;
|
sram_addr <= mpu_sram_address;
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sram_oe_n <= mpu_sram_oe_n;
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sram_oe_n <= mpu_sram_oe_n;
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sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
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sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
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sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
|
sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
|
sram_ce_n <= '0';
|
sram_ce_n <= '0';
|
sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
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sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
|
|
|
|
|
--##############################################################################
|
--##############################################################################
|
-- RESET, CLOCK
|
-- RESET, CLOCK
|
--##############################################################################
|
--##############################################################################
|
|
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-- Use button 3 as reset
|
-- Use button 3 as reset
|
reset <= not buttons(3);
|
reset_synchronization:
|
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process(clk)
|
|
begin
|
|
if clk'event and clk='1' then
|
|
reset_sync(2) <= not buttons(3);
|
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reset_sync(1) <= reset_sync(2);
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reset_sync(0) <= reset_sync(1);
|
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end if;
|
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end process reset_synchronization;
|
|
|
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reset <= reset_sync(0);
|
|
|
|
|
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
|
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
|
process(clk_50MHz)
|
process(clk_50MHz)
|
begin
|
begin
|
if clk_50MHz'event and clk_50MHz='1' then
|
if clk_50MHz'event and clk_50MHz='1' then
|
if reset = '1' then
|
if reset = '1' then
|
clk_1hz <= '0';
|
clk_1hz <= '0';
|
counter_1hz <= (others => '0');
|
counter_1hz <= (others => '0');
|
else
|
else
|
if conv_integer(counter_1hz) = 50000000 then
|
if conv_integer(counter_1hz) = 50000000 then
|
counter_1hz <= (others => '0');
|
counter_1hz <= (others => '0');
|
clk_1hz <= not clk_1hz;
|
clk_1hz <= not clk_1hz;
|
else
|
else
|
counter_1hz <= counter_1hz + 1;
|
counter_1hz <= counter_1hz + 1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Master clock is external 50MHz oscillator
|
-- Master clock is external 50MHz oscillator
|
clk <= clk_50MHz;
|
clk <= clk_50MHz;
|
|
|
|
|
--##############################################################################
|
--##############################################################################
|
-- LEDS, SWITCHES
|
-- LEDS, SWITCHES
|
--##############################################################################
|
--##############################################################################
|
|
|
-- Display the contents of a debug register at the green leds bar
|
-- Display the contents of a debug register at the green leds bar
|
green_leds <= reg_gleds;
|
green_leds <= reg_gleds;
|
|
|
|
|
--##############################################################################
|
--##############################################################################
|
-- QUAD 7-SEGMENT DISPLAYS
|
-- QUAD 7-SEGMENT DISPLAYS
|
--##############################################################################
|
--##############################################################################
|
|
|
-- So far, nothing to display
|
-- Show contents of debug register in hex display
|
display_data <= reg_display;
|
display_data <= reg_display;
|
|
|
|
|
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
|
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
|
with display_data(15 downto 12) select hex3 <=
|
hex3 <= nibble_to_7seg(display_data(15 downto 12));
|
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
|
hex2 <= nibble_to_7seg(display_data(11 downto 8));
|
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
|
hex1 <= nibble_to_7seg(display_data( 7 downto 4));
|
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
|
hex0 <= nibble_to_7seg(display_data( 3 downto 0));
|
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
|
|
|
|
with display_data(11 downto 8) select hex2 <=
|
|
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
|
|
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
|
|
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
|
|
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
|
|
|
|
with display_data(7 downto 4) select hex1 <=
|
|
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
|
|
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
|
|
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
|
|
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
|
|
|
|
with display_data(3 downto 0) select hex0 <=
|
|
"0000001" when X"0","1001111" when X"1","0010010" when X"2","0000110" when X"3",
|
|
"1001100" when X"4","0100100" when X"5","0100000" when X"6","0001111" when X"7",
|
|
"0000000" when X"8","0000100" when X"9","0001000" when X"a","1100000" when X"b",
|
|
"0110001" when X"c","1000010" when X"d","0110000" when X"e","0111000" when others;
|
|
|
|
--##############################################################################
|
--##############################################################################
|
-- SD card interface
|
-- SD card interface
|
--##############################################################################
|
--##############################################################################
|
|
|
-- unused in this demo, but I did not bother to cut away the attached registers
|
-- unused in this demo
|
sd_cs <= '0';
|
sd_cs <= '0';
|
sd_cmd <= '0';
|
sd_cmd <= '0';
|
sd_clk <= '0';
|
sd_clk <= '0';
|
sd_in <= 'Z';
|
sd_in <= 'Z';
|
|
|
|
|
--##############################################################################
|
--##############################################################################
|
-- SERIAL
|
-- SERIAL
|
--##############################################################################
|
--##############################################################################
|
|
|
-- Embedded in the MPU entity
|
-- Embedded in the MPU entity
|
|
|
end minimal;
|
end minimal;
|
|
|
