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-- mips_alu.vhdl -- integer arithmetic ALU, excluding mult/div functionality.
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-- mips_alu.vhdl -- integer arithmetic ALU, excluding mult/div functionality.
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright (C) 2010 Jose A. Ruiz
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-- Copyright (C) 2011 Jose A. Ruiz
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--
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--
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-- This source file may be used and distributed without
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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-- the original copyright notice and the associated disclaimer.
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--
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--
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-- This source file is free software; you can redistribute it
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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-- later version.
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--
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--
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-- This source is distributed in the hope that it will be
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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-- details.
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--
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--
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-- You should have received a copy of the GNU Lesser General
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-- from http://www.opencores.org/lgpl.shtml
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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entity mips_alu is
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entity mips_alu is
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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-- function selection
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-- function selection
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ac : in t_alu_control;
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ac : in t_alu_control;
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-- comparison result flags
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-- comparison result flags
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flags : out t_alu_flags;
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flags : out t_alu_flags;
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-- data inputs
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-- data inputs
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inp1 : in std_logic_vector(31 downto 0);
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inp1 : in std_logic_vector(31 downto 0);
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inp2 : in std_logic_vector(31 downto 0);
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inp2 : in std_logic_vector(31 downto 0);
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-- data result output
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-- data result output
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outp : out std_logic_vector(31 downto 0)
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outp : out std_logic_vector(31 downto 0)
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);
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);
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end;
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end;
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architecture rtl of mips_alu is
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architecture rtl of mips_alu is
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subtype t_eword is std_logic_vector(32 downto 0);
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subtype t_eword is std_logic_vector(32 downto 0);
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signal inp2_neg : t_word;
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signal inp2_neg : t_word;
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signal alu_eop1, alu_eop2 : t_eword;
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signal alu_eop1, alu_eop2 : t_eword;
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signal sex1, sex2 : std_logic;
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signal sex1, sex2 : std_logic;
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signal alu_arith : t_eword;
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signal alu_arith : t_eword;
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signal alu_shift : t_word;
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signal alu_shift : t_word;
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signal alu_logic_shift : t_word;
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signal alu_logic_shift : t_word;
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signal alu_logic : t_word;
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signal alu_logic : t_word;
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signal less_than_zero : std_logic;
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signal less_than_zero : std_logic;
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signal final_mux_sel : std_logic_vector(1 downto 0);
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signal final_mux_sel : std_logic_vector(1 downto 0);
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signal alu_temp : t_word;
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signal alu_temp : t_word;
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begin
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begin
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with ac.neg_sel select inp2_neg <=
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with ac.neg_sel select inp2_neg <=
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not inp2 when "01", -- nor, sub, etc.
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not inp2 when "01", -- nor, sub, etc.
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inp2(15 downto 0) & X"0000" when "10", -- lhi
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inp2(15 downto 0) & X"0000" when "10", -- lhi
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X"00000000" when "11", -- zero
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X"00000000" when "11", -- zero
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inp2 when others; -- straight
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inp2 when others; -- straight
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sex1 <= inp1(31) when ac.arith_unsigned='0' else '0';
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sex1 <= inp1(31) when ac.arith_unsigned='0' else '0';
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alu_eop1 <= sex1 & inp1;
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alu_eop1 <= sex1 & inp1;
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sex2 <= inp2_neg(31) when (ac.arith_unsigned='0' or ac.use_slt='1') else '0';
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sex2 <= inp2_neg(31) when (ac.arith_unsigned='0' or ac.use_slt='1') else '0';
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alu_eop2 <= sex2 & inp2_neg;
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alu_eop2 <= sex2 & inp2_neg;
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alu_arith <= alu_eop1 + alu_eop2 + ac.cy_in;
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alu_arith <= alu_eop1 + alu_eop2 + ac.cy_in;
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with ac.logic_sel select alu_logic <=
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with ac.logic_sel select alu_logic <=
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inp1 and inp2_neg when "00",
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inp1 and inp2_neg when "00",
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inp1 or inp2_neg when "01",
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inp1 or inp2_neg when "01",
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inp1 xor inp2_neg when "10",
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inp1 xor inp2_neg when "10",
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inp2_neg when others;
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inp2_neg when others;
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shifter : entity work.mips_shifter
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shifter : entity work.mips_shifter
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port map (
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port map (
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d => inp2,
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d => inp2,
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a => ac.shift_amount,
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a => ac.shift_amount,
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fn => ac.shift_sel,
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fn => ac.shift_sel,
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r => alu_shift
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r => alu_shift
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);
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);
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with ac.use_logic select alu_logic_shift <=
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with ac.use_logic select alu_logic_shift <=
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alu_logic when "01",
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alu_logic when "01",
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not alu_logic when "11", -- used only by NOR instruction
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not alu_logic when "11", -- used only by NOR instruction
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alu_shift when others;
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alu_shift when others;
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final_mux_sel(0) <= ac.use_arith when ac.use_slt='0' else less_than_zero;
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final_mux_sel(0) <= ac.use_arith when ac.use_slt='0' else less_than_zero;
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final_mux_sel(1) <= ac.use_slt;
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final_mux_sel(1) <= ac.use_slt;
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with final_mux_sel select alu_temp <=
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with final_mux_sel select alu_temp <=
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alu_arith(31 downto 0) when "01",
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alu_arith(31 downto 0) when "01",
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alu_logic_shift when "00",
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alu_logic_shift when "00",
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X"00000001" when "11",
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X"00000001" when "11",
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X"00000000" when others;
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X"00000000" when others;
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less_than_zero <= alu_arith(32);
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less_than_zero <= alu_arith(32);
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flags.inp1_lt_zero <= inp1(31);
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flags.inp1_lt_zero <= inp1(31);
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flags.inp1_lt_inp2 <= less_than_zero;
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flags.inp1_lt_inp2 <= less_than_zero;
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flags.inp1_eq_inp2 <= '1' when alu_arith(31 downto 0)=X"00000000" else '0';
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flags.inp1_eq_inp2 <= '1' when alu_arith(31 downto 0)=X"00000000" else '0';
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flags.inp1_eq_zero <= '1' when inp1(31 downto 0)=X"00000000" else '0'; -- FIXME simplify
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flags.inp1_eq_zero <= '1' when inp1(31 downto 0)=X"00000000" else '0'; -- FIXME simplify
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outp <= alu_temp;
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outp <= alu_temp;
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end; --architecture rtl
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end; --architecture rtl
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