--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
|
-- mips_mult.vhdl -- multiplier from Plasma project, slightly modified.
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-- mips_mult.vhdl -- multiplier from Plasma project, slightly modified.
|
--
|
--
|
-- The original file from Plasma has been adapted to the Ion core. Changes are
|
-- The original file from Plasma has been adapted to the Ion core. Changes are
|
-- tagged with '@ion'. There are a few notes at the end of the file with the
|
-- tagged with '@ion'. There are a few notes at the end of the file with the
|
-- rationale for the changes -- useful only if any trouble shows up later.
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-- rationale for the changes -- useful only if any trouble shows up later.
|
-- The structure has not changed, only a few implementation details.
|
-- The structure has not changed, only a few implementation details.
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- TITLE: Multiplication and Division Unit
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-- TITLE: Multiplication and Division Unit
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- DATE CREATED: 1/31/01
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-- FILENAME: mult.vhd
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-- FILENAME: mult.vhd
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-- PROJECT: Plasma CPU core
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- COPYRIGHT: Software placed into the public domain by the author.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- Software 'as is' without warranty. Author liable for nothing.
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-- DESCRIPTION:
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-- DESCRIPTION:
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-- Implements the multiplication and division unit in 32 clocks.
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-- Implements the multiplication and division unit in 32 clocks.
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--
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--
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-- To reduce space, compile your code using the flag "-mno-mul" which
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-- To reduce space, compile your code using the flag "-mno-mul" which
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-- will use software base routines in math.c if USE_SW_MULT is defined.
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-- will use software base routines in math.c if USE_SW_MULT is defined.
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-- Then remove references to the entity mult in mlite_cpu.vhd.
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-- Then remove references to the entity mult in mlite_cpu.vhd.
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--
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--
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-- MULTIPLICATION
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-- MULTIPLICATION
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-- long64 answer = 0
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-- long64 answer = 0
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-- for(i = 0; i < 32; ++i)
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-- for(i = 0; i < 32; ++i)
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-- {
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-- {
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
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-- b = b >> 1;
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-- b = b >> 1;
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-- }
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-- }
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--
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--
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-- DIVISION
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-- DIVISION
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-- long upper=a, lower=0;
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-- long upper=a, lower=0;
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-- a = b << 31;
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-- a = b << 31;
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-- for(i = 0; i < 32; ++i)
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-- for(i = 0; i < 32; ++i)
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-- {
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-- {
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-- lower = lower << 1;
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-- lower = lower << 1;
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-- if(upper >= a && a && b < 2)
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-- if(upper >= a && a && b < 2)
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-- {
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-- {
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-- upper = upper - a;
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-- upper = upper - a;
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-- lower |= 1;
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-- lower |= 1;
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-- }
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-- }
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-- a = ((b&2) << 30) | (a >> 1);
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-- a = ((b&2) << 30) | (a >> 1);
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-- b = b >> 1;
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-- b = b >> 1;
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-- }
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-- }
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_arith.all;
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use work.mips_pkg.all;
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use work.mips_pkg.all;
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|
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entity mips_mult is
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entity mips_mult is
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generic(mult_type : string := "DEFAULT");
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generic(mult_type : string := "DEFAULT");
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port(clk : in std_logic;
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port(clk : in std_logic;
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reset_in : in std_logic;
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reset_in : in std_logic;
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a, b : in std_logic_vector(31 downto 0);
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a, b : in std_logic_vector(31 downto 0);
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mult_func : in t_mult_function;
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mult_func : in t_mult_function;
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c_mult : out std_logic_vector(31 downto 0);
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c_mult : out std_logic_vector(31 downto 0);
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pause_out : out std_logic);
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pause_out : out std_logic);
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end; --entity mult
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end; --entity mult
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|
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architecture logic of mips_mult is
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architecture logic of mips_mult is
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|
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constant MODE_MULT : std_logic := '1';
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constant MODE_MULT : std_logic := '1';
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constant MODE_DIV : std_logic := '0';
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constant MODE_DIV : std_logic := '0';
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|
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signal mode_reg : std_logic;
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signal mode_reg : std_logic;
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signal negate_reg : std_logic;
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signal negate_reg : std_logic;
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signal sign_reg : std_logic;
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signal sign_reg : std_logic;
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signal sign2_reg : std_logic;
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signal sign2_reg : std_logic;
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signal count_reg : std_logic_vector(5 downto 0);
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signal count_reg : std_logic_vector(5 downto 0);
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signal aa_reg : std_logic_vector(31 downto 0);
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signal aa_reg : std_logic_vector(31 downto 0);
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signal bb_reg : std_logic_vector(31 downto 0);
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signal bb_reg : std_logic_vector(31 downto 0);
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signal upper_reg : std_logic_vector(31 downto 0);
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signal upper_reg : std_logic_vector(31 downto 0);
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signal lower_reg : std_logic_vector(31 downto 0);
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signal lower_reg : std_logic_vector(31 downto 0);
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|
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signal a_neg : std_logic_vector(31 downto 0);
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signal a_neg : std_logic_vector(31 downto 0);
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signal b_neg : std_logic_vector(31 downto 0);
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signal b_neg : std_logic_vector(31 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal sum : std_logic_vector(32 downto 0);
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signal sum_a : std_logic_vector(32 downto 0);
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signal sum_a : std_logic_vector(32 downto 0);
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signal sum_b : std_logic_vector(32 downto 0);
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signal sum_b : std_logic_vector(32 downto 0);
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|
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begin
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begin
|
|
|
-- @ion Output mux no longer uses function bv_negate. Removing one input that
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-- @ion Output mux no longer uses function bv_negate. Removing one input that
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-- is no longer needed, even if constant, may help in some FPGA architectures
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-- is no longer needed, even if constant, may help in some FPGA architectures
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-- too.
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-- too.
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-- See @note2
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-- See @note2
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-- Result
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-- Result
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c_mult <= lower_reg when mult_func = MULT_READ_LO and
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c_mult <= lower_reg when mult_func = MULT_READ_LO and
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negate_reg = '0' else
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negate_reg = '0' else
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not(lower_reg) + 1 when mult_func = MULT_READ_LO and
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not(lower_reg) + 1 when mult_func = MULT_READ_LO and
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--bv_negate(lower_reg) when mult_func = MULT_READ_LO and
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--bv_negate(lower_reg) when mult_func = MULT_READ_LO and
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negate_reg = '1' else
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negate_reg = '1' else
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upper_reg; -- when mult_func = MULT_READ_HI else
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upper_reg; -- when mult_func = MULT_READ_HI else
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--ZERO;
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--ZERO;
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|
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-- @ion Stall pipeline while operation completes even if output is not needed
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-- @ion Stall pipeline while operation completes even if output is not needed
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-- immediately.
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-- immediately.
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-- See @note3
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-- See @note3
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pause_out <= '1' when (count_reg(5 downto 0) /= "000000") else '0'; --and
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pause_out <= '1' when (count_reg(5 downto 0) /= "000000") else '0'; --and
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--(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
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--(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
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|
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-- ABS and remainder signals
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-- ABS and remainder signals
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a_neg <= not(a) + 1; --bv_negate(a); -- @ion @note2
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a_neg <= not(a) + 1; --bv_negate(a); -- @ion @note2
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b_neg <= not(b) + 1; --bv_negate(b); -- @ion @note2
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b_neg <= not(b) + 1; --bv_negate(b); -- @ion @note2
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|
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-- @ion Replaced function bv_adder with straight vector code
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-- @ion Replaced function bv_adder with straight vector code
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--sum <= bv_adder(upper_reg, aa_reg, mode_reg);
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--sum <= bv_adder(upper_reg, aa_reg, mode_reg);
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sum_a <= ('0' & upper_reg); -- No sign extension: MSB of sum is special
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sum_a <= ('0' & upper_reg); -- No sign extension: MSB of sum is special
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sum_b <= ('0' & aa_reg);
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sum_b <= ('0' & aa_reg);
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with mode_reg select sum <=
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with mode_reg select sum <=
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sum_a + sum_b when '1',
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sum_a + sum_b when '1',
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sum_a - sum_b when others;
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sum_a - sum_b when others;
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|
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--multiplication/division unit
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--multiplication/division unit
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mult_proc: process(clk, reset_in, a, b, mult_func,
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mult_proc: process(clk, reset_in, a, b, mult_func,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
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variable count : std_logic_vector(2 downto 0);
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variable count : std_logic_vector(2 downto 0);
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begin
|
begin
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count := "001";
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count := "001";
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-- @ion Old asynchronous reset converted to synchronous, for consistency
|
|
-- (Code indenting mangled by the new 'if' level)
|
|
--if reset_in = '1' then
|
|
if rising_edge(clk) then
|
if reset_in = '1' then
|
if reset_in = '1' then
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mode_reg <= '0';
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mode_reg <= '0';
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negate_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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sign2_reg <= '0';
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count_reg <= "000000";
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count_reg <= "000000";
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aa_reg <= ZERO;
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aa_reg <= ZERO;
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bb_reg <= ZERO;
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bb_reg <= ZERO;
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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lower_reg <= ZERO;
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lower_reg <= ZERO;
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elsif rising_edge(clk) then
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--elsif rising_edge(clk) then
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|
else
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case mult_func is
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case mult_func is
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when MULT_WRITE_LO =>
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when MULT_WRITE_LO =>
|
lower_reg <= a;
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lower_reg <= a;
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_WRITE_HI =>
|
when MULT_WRITE_HI =>
|
upper_reg <= a;
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upper_reg <= a;
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_MULT =>
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when MULT_MULT =>
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mode_reg <= MODE_MULT;
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mode_reg <= MODE_MULT;
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aa_reg <= a;
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aa_reg <= a;
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bb_reg <= b;
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bb_reg <= b;
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upper_reg <= ZERO;
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upper_reg <= ZERO;
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= '0';
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negate_reg <= '0';
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sign_reg <= '0';
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sign_reg <= '0';
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sign2_reg <= '0';
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sign2_reg <= '0';
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when MULT_SIGNED_MULT =>
|
when MULT_SIGNED_MULT =>
|
mode_reg <= MODE_MULT;
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mode_reg <= MODE_MULT;
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if b(31) = '0' then
|
if b(31) = '0' then
|
aa_reg <= a;
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aa_reg <= a;
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bb_reg <= b;
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bb_reg <= b;
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sign_reg <= a(31);
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sign_reg <= a(31);
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else
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else
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aa_reg <= a_neg;
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aa_reg <= a_neg;
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bb_reg <= b_neg;
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bb_reg <= b_neg;
|
sign_reg <= a_neg(31);
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sign_reg <= a_neg(31);
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end if;
|
end if;
|
sign2_reg <= '0';
|
sign2_reg <= '0';
|
upper_reg <= ZERO;
|
upper_reg <= ZERO;
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count_reg <= "100000";
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count_reg <= "100000";
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negate_reg <= '0';
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negate_reg <= '0';
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when MULT_DIVIDE =>
|
when MULT_DIVIDE =>
|
mode_reg <= MODE_DIV;
|
mode_reg <= MODE_DIV;
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aa_reg <= b(0) & ZERO(30 downto 0);
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aa_reg <= b(0) & ZERO(30 downto 0);
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bb_reg <= b;
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bb_reg <= b;
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upper_reg <= a;
|
upper_reg <= a;
|
count_reg <= "100000";
|
count_reg <= "100000";
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negate_reg <= '0';
|
negate_reg <= '0';
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when MULT_SIGNED_DIVIDE =>
|
when MULT_SIGNED_DIVIDE =>
|
mode_reg <= MODE_DIV;
|
mode_reg <= MODE_DIV;
|
if b(31) = '0' then
|
if b(31) = '0' then
|
aa_reg(31) <= b(0);
|
aa_reg(31) <= b(0);
|
bb_reg <= b;
|
bb_reg <= b;
|
else
|
else
|
aa_reg(31) <= b_neg(0);
|
aa_reg(31) <= b_neg(0);
|
bb_reg <= b_neg;
|
bb_reg <= b_neg;
|
end if;
|
end if;
|
if a(31) = '0' then
|
if a(31) = '0' then
|
upper_reg <= a;
|
upper_reg <= a;
|
else
|
else
|
upper_reg <= a_neg;
|
upper_reg <= a_neg;
|
end if;
|
end if;
|
aa_reg(30 downto 0) <= ZERO(30 downto 0);
|
aa_reg(30 downto 0) <= ZERO(30 downto 0);
|
count_reg <= "100000";
|
count_reg <= "100000";
|
negate_reg <= a(31) xor b(31);
|
negate_reg <= a(31) xor b(31);
|
when others =>
|
when others =>
|
|
|
if count_reg /= "000000" then
|
if count_reg /= "000000" then
|
if mode_reg = MODE_MULT then
|
if mode_reg = MODE_MULT then
|
-- Multiplication
|
-- Multiplication
|
if bb_reg(0) = '1' then
|
if bb_reg(0) = '1' then
|
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
|
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
|
lower_reg <= sum(0) & lower_reg(31 downto 1);
|
lower_reg <= sum(0) & lower_reg(31 downto 1);
|
sign2_reg <= sign2_reg or sign_reg;
|
sign2_reg <= sign2_reg or sign_reg;
|
sign_reg <= '0';
|
sign_reg <= '0';
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
-- The following six lines are optional for speedup
|
-- The following six lines are optional for speedup
|
--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
|
--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
|
-- count_reg(5 downto 2) /= "0000" then
|
-- count_reg(5 downto 2) /= "0000" then
|
-- upper_reg <= "0000" & upper_reg(31 downto 4);
|
-- upper_reg <= "0000" & upper_reg(31 downto 4);
|
-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
|
-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
|
-- count := "100";
|
-- count := "100";
|
-- bb_reg <= "0000" & bb_reg(31 downto 4);
|
-- bb_reg <= "0000" & bb_reg(31 downto 4);
|
else
|
else
|
upper_reg <= sign2_reg & upper_reg(31 downto 1);
|
upper_reg <= sign2_reg & upper_reg(31 downto 1);
|
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
|
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
end if;
|
end if;
|
else
|
else
|
-- Division
|
-- Division
|
if sum(32) = '0' and aa_reg /= ZERO and
|
if sum(32) = '0' and aa_reg /= ZERO and
|
bb_reg(31 downto 1) = ZERO(31 downto 1) then
|
bb_reg(31 downto 1) = ZERO(31 downto 1) then
|
upper_reg <= sum(31 downto 0);
|
upper_reg <= sum(31 downto 0);
|
lower_reg(0) <= '1';
|
lower_reg(0) <= '1';
|
else
|
else
|
lower_reg(0) <= '0';
|
lower_reg(0) <= '0';
|
end if;
|
end if;
|
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
|
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
|
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
|
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
bb_reg <= '0' & bb_reg(31 downto 1);
|
end if;
|
end if;
|
count_reg <= count_reg - count;
|
count_reg <= count_reg - count;
|
end if; --count
|
end if; --count
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
end if;
|
|
|
end process;
|
end process;
|
|
|
end; --architecture logic
|
end; --architecture logic
|
|
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
-- @note1 : bv_adder function removed
|
-- @note1 : bv_adder function removed
|
-- This function was a slightly modified adder/substractor coded in a bitwise
|
-- This function was a slightly modified adder/substractor coded in a bitwise
|
-- manner that made it hard for synth tools to recognize it as such. At least
|
-- manner that made it hard for synth tools to recognize it as such. At least
|
-- that's what I think. Replacing it with straigth code results in smaller and
|
-- that's what I think. Replacing it with straigth code results in smaller and
|
-- faster logic (about 23% faster).
|
-- faster logic (about 23% faster).
|
--
|
--
|
-- @note2 : bv_negate function removed
|
-- @note2 : bv_negate function removed
|
-- This function computed a 2's complement bitwise. Removed on the same grounds
|
-- This function computed a 2's complement bitwise. Removed on the same grounds
|
-- as @note1 but with no apparent improvement in synthesis results.
|
-- as @note1 but with no apparent improvement in synthesis results.
|
--
|
--
|
-- @note3 : pause_out active until operation complete
|
-- @note3 : pause_out active until operation complete
|
-- The original Plasma module allowed the pipeline and the multiplier to run
|
-- The original Plasma module allowed the pipeline and the multiplier to run
|
-- concurrently until the multiplier result was needed, and only then the
|
-- concurrently until the multiplier result was needed, and only then the
|
-- pipeline was stalled.
|
-- pipeline was stalled if the mul/div operation had not finished yet.
|
-- We want to make sure we can abort a mul/div so for the time being we stall
|
-- We want to make sure we can abort a mul/div so for the time being we stall
|
-- until the operation is complete.
|
-- until the operation is complete.
|
-- note that if we later want to change this, the parent module will need
|
-- I *think* that's what the libraries and the toolchain assume anyway.
|
|
-- Note that if we later want to change this, the parent module will need
|
-- changes too (logic for p1_muldiv_running).
|
-- changes too (logic for p1_muldiv_running).
|
|
|