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-- mips_shifter.vhdl -- combinational barrel shifter
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-- mips_shifter.vhdl -- combinational barrel shifter
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--
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--
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Copyright (C) 2010 Jose A. Ruiz
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-- Copyright (C) 2011 Jose A. Ruiz
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--
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--
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-- This source file may be used and distributed without
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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-- the original copyright notice and the associated disclaimer.
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--
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--
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-- This source file is free software; you can redistribute it
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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-- later version.
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--
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--
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-- This source is distributed in the hope that it will be
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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-- details.
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--
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--
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-- You should have received a copy of the GNU Lesser General
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-- from http://www.opencores.org/lgpl.shtml
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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entity mips_shifter is
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entity mips_shifter is
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port(
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port(
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-- data input
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-- data input
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d : in std_logic_vector(31 downto 0);
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d : in std_logic_vector(31 downto 0);
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-- shift amount
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-- shift amount
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a : in std_logic_vector(4 downto 0);
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a : in std_logic_vector(4 downto 0);
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-- shift function: {0=sll,1=sla(unused),2=srl,3=sra}
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-- shift function: {0=sll,1=sla(unused),2=srl,3=sra}
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fn : in std_logic_vector(1 downto 0);
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fn : in std_logic_vector(1 downto 0);
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-- shift result
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-- shift result
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r : out std_logic_vector(31 downto 0)
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r : out std_logic_vector(31 downto 0)
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);
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);
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end;
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end;
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architecture small of mips_shifter is
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architecture small of mips_shifter is
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signal i_rev, o_rev : std_logic_vector(31 downto 0);
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signal i_rev, o_rev : std_logic_vector(31 downto 0);
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signal ext : std_logic_vector(31 downto 0);
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signal ext : std_logic_vector(31 downto 0);
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type t_s is array(0 to 5) of std_logic_vector(31 downto 0);
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type t_s is array(0 to 5) of std_logic_vector(31 downto 0);
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signal s : t_s;
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signal s : t_s;
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begin
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begin
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-- The barrel shifter needs to shift left and right. This would usually
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-- The barrel shifter needs to shift left and right. This would usually
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-- require two parallel barrel shifters (left and right) and an output mux
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-- require two parallel barrel shifters (left and right) and an output mux
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-- stage. Instead, we're gonna use a single left shifter, with two
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-- stage. Instead, we're gonna use a single left shifter, with two
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-- conditional bit-reversal stages at input and output.
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-- conditional bit-reversal stages at input and output.
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-- This will increase the LUT depth (and thus the delay) by 1 LUT row but
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-- This will increase the LUT depth (and thus the delay) by 1 LUT row but
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-- we'll cut the area by 4/11 more or less (depends on how many dedicated
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-- we'll cut the area by 4/11 more or less (depends on how many dedicated
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-- muxes vs. LUTs the synth will use).
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-- muxes vs. LUTs the synth will use).
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-- The barrel shifter can account for as much as 1/4 of the CPU area
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-- The barrel shifter can account for as much as 1/4 of the CPU area
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-- (excluding mult/div unit) so it makes sense to be cheap here if what we
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-- (excluding mult/div unit) so it makes sense to be cheap here if what we
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-- want is a small core.
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-- want is a small core.
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-- NOTE: this logic may or may not be in the critical delay path of the
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-- NOTE: this logic may or may not be in the critical delay path of the
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-- core, depending on the cache implementation. See your synthesis report.
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-- core, depending on the cache implementation. See your synthesis report.
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-- Reverse input when shifting right
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-- Reverse input when shifting right
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input_reversed:
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input_reversed:
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for i in 0 to 31 generate
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for i in 0 to 31 generate
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begin
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begin
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i_rev(i) <= d(31-i);
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i_rev(i) <= d(31-i);
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end generate input_reversed;
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end generate input_reversed;
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s(5) <= i_rev when fn(1)='1' else d;
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s(5) <= i_rev when fn(1)='1' else d;
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-- Sign extension / zero extension
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-- Sign extension / zero extension
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ext <= (others => d(31)) when fn(0)='1' else (others => '0');
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ext <= (others => d(31)) when fn(0)='1' else (others => '0');
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-- Build left barrel shifter in 5 binary stages as usual
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-- Build left barrel shifter in 5 binary stages as usual
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shifter_stages:
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shifter_stages:
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for i in 0 to 4 generate
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for i in 0 to 4 generate
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begin
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begin
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with a(i) select s(i) <=
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with a(i) select s(i) <=
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s(i+1)(31-2**i downto 0) & ext(2**i-1 downto 0) when '1',
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s(i+1)(31-2**i downto 0) & ext(2**i-1 downto 0) when '1',
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s(i+1) when others;
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s(i+1) when others;
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end generate shifter_stages;
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end generate shifter_stages;
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-- Reverse output when shifting right
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-- Reverse output when shifting right
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output_reversal:
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output_reversal:
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for i in 0 to 31 generate
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for i in 0 to 31 generate
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begin
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begin
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o_rev(i) <= s(0)(31-i);
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o_rev(i) <= s(0)(31-i);
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end generate output_reversal;
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end generate output_reversal;
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r <= o_rev when fn(1)='1' else s(0);
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r <= o_rev when fn(1)='1' else s(0);
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end architecture small;
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end architecture small;
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